DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked

本文详细讲述了在基于微控制器IP核PSTN短消息终端SoC设计中软硬件协同设计的方法。在合理划分硬件和软件任务的基础上，使设计更好地达到了系统性能的要求。

介绍在基于微控制器IP核的PSTN短消息终端SoC设计当中，如何合理划分硬件和软件的功能；从对微控制器IP核的配置与扩展、片上外设在SFR总线上的映射、存储空间的划分与映射等三个方面，详细讲述SoC的软硬件协同设计。