SystemVerilog 3.1a Language Reference Manual Accellera's Extension to Verilog. Table of Contents Section 1 Introduction to SystemVerilog ...................................................................................................... 1 Section
The JESD79-3 document defines DDR3L SDRAM, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments with the exception of what is stated within this standard.
a set of extensions to the IEEE 1364-2001 Verilog Hardware Descr iption Language to aid in the creation and verification of abstract architectural level models
JESD79-3-1A-01_DDR3L_May_2013, Addendum No. 1 to JESD79‐3 ‐ 1.35 V DDR3L‐800, DDR3L‐1066, DDR3L‐1333, DDR3L‐1600, and (Minor Editorial Revision of JESD79‐3‐1A, January 2013) DDR3L‐1866, (Minor Editorial Revision of JESD79‐3‐1A, January 2013)
