This document describes a High-Speed serial interface called C-PHY, which provides high throughput 2 performance over bandwidth limited channels for connecting to peripherals, including displays and cameras.
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MIPI C-PHY is developed by the MIPI PHY Working Group. Operation and available data rates for a link can be asymmetrical, which enables implementers to optimize the transfer rates to system needs. Bi-directional and half-duplex operation are optiona
Agenda – MIPI Overview, history and recent changes – RX test: recap of methodology – M-PHY key features, changes in spec & methodology – D-PHY recap of basics, signaling, LP- and HS- modes – C-PHY intro on 3-wire 3-level signaling – Keysight test so
