FIFOs are often used to safely pass data from one clock domain to another asynchronous clock domain. Using aFIFO to pass data from one clock domain to another clock domain requires multi-asynchronous clock designtechniques. There are many way s to d
异步FIFO Designing a FIFO is one of the most common problems an ASIC designer comes across. This series of articles is aimed at looking at how FIFOs may be designed -- a task that is not as simple as it seems.
