The PHY Interface for the PCI Express Architecture (PIPE) is intended to enable the development of functionally equivalent PCI Express PHY's. Such PHY's can be delivered as discrete IC's or as macrocells for inclusion in ASIC designs. The specificat
QSGMII uses two data signals in each direction to convey frame data and link rate information between a multi-port 10/100/1000 PHY and Ethernet MAC. The data signals operate at 5.0 Gbps using CDR technology to recover the clock at the MAC and PHY in
IEEE Standard for Information technology— Telecommunications and information exchange between systems— Local and metropolitan area networks— Specific requirements Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Wirel
