详细讲述lpc总线的细节，可供开发参考。 This document contains a specification for a new low pin count bus interface, called LPC. The target audiences for this document are system and component designers.
RMII specification, This document comprises a low pin count Reduced Media Independent InterfaceTM (RMIITM) specification intended for use between Ethernet PHYs and Switch ASICs.
This specification defines a high-speed serialized ATA data link interface (specifying Phy, Link, Transport, and Application layers). The serialized interface uses the command set from the ATA/ATAPI-6 standard, augmented with Native Command Queuing
飞思卡尔 IMX6Q iomux_tool_v3.4硬件接口资源配置工具 i.MX IOMUX Design Aid (User’s Guide for IOMux.exe) by David DiCarlo Multimedia Applications Division Freescale Semiconductor, Inc. Austin, TX Package pin count limitations require each device in the i.MX family t
MIPI M-PHY 最新规范，This document describes a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applications to obtain low pin count combined with very good power efficiency. It is targeted to be su
BCM5461S详细设计开发资料。 BCM5461S SUPPORTED SWITCH/MAC INTERFACES: • GMII (Gigabit Media Independent Interface): 1000-Mbps data rate (designed for 2.5V or 3.3V I/O operation) • MII (Media Independent Interface): 100/10-Mbps data rates (designed for 2.5V or
Altera’s MAX® 10 FPGAs revolutionize non-volatile integration by delivering advanced processing capabilities in a low-cost, single chip small form factor programmable logic device. Building upon the single chip heritage of previous MAX device famili
The DM9000C is a fully intergrated and cost-effective low pin count single chip Fast Ethernet controller with a general processor interface, a 10/100M PHY and 4K Dword SRAM.It is designed with low power and high performance process interface that sup
用于USB3300设计的详细说明文档，包含模式和阻抗配置的寄存器说明等。
The USB3300 is an industrial temperature Hi-Speed USB Physical Layer Transceiver (PHY). The USB3300 uses a low pin count interface (ULPI) to connect to a ULPI compliant Link layer. The ULPI interface reduces the U
