This paper describes an I/O scheme for use in a highspeed bus which eliminates setup and hold time requirements between clock and data by using an oversampling method. The I/O circuit uses a low jitter phase-locked loop (PLL) which suppresses the ef

1 Introduction and Overview Thucydides Xanthopoulos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 The Clock Design Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Abstract—Domino circuits are widely used in high-performance CMOS microprocessors. However, textbook domino pipelines suffer significant timing overhead from clock skew, latch delay, and the inability to borrow time. To eliminate this overhead, some