This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL Testbench files. This files only include t
nRF51 SDK v10.0.0 ----------------- Release Date: Week 46 Highlights: - New BLE Peer Manager (experimental), replacement for the BLE Device Manager - FreeRTOS support - New ANT modules, additional examples, and new and expanded ANT+ profiles - Suppo
分享Cypress_CYUSB3014_KIT开发套件光盘资料共分三部分。而这部分为Altera_cyclone III -DDR2文件资料，和Cypress_CYUSB3014_KIT同一开发板。资料可了解基于FPGA和CYUSB3014组成USB3.0采集传输系统的一般电路原理，其充分发挥USB3.0芯片的特性，特将CYUSB3014芯片的所有数字IO与FPGA连接，包括32根数据线，13根控制线、4根I2S信号线以及UART线。CYUSB3014功能包含时钟晶振、复位、时钟源配置、引导方式
