Software Optimization Reference Manual，包含10th-generation-intel-core-processor-throughput-and-latency.zip, 64-IA-32-architectures-optimization-manual.pdf,intel-Xeon-scalable-process-throughput-latency.pdf。

一种FPGA硬件加速方案，实现深度学习，可实现高吞吐量的CNN网络Session 3: Deep Learning FPGA 18, February 25-27, Monterey, CA, USA maps. Let b, n and m index into the Batch, fin and fout dimensions Table 1: Variation of model paramcters Equation 4 specifies the operations of a co

The table describes throughput and latency for processors with two FMA units, assuming all sources come from the FMA unit. See FMA latency chapter in the optimization guide for more information. Memory latencies are assuming Data Cache Unit (DCU) hit