This paper describes an I/O scheme for use in a highspeed bus which eliminates setup and hold time requirements between clock and data by using an oversampling method. The I/O circuit uses a low jitter phase-locked loop (PLL) which suppresses the ef
This paper presents analyses and experimental results on the jitter transfer of delay-locked loops (DLLs). Through a -domain model, we showthat in a widely used DLL configuration,jitter peaking always exists and high-frequency jitter does not get at
