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应用于 2.4 及5.7GHz 802.11 WLAN 之CMOS 单晶片射频集成电路
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上传时间: 2010-06-23
详细说明： 成功大学硕士论文 This thesis presents the development of 5.7 GHz CMOS RFICs for the IEEE 802.11a WLAN RF receiver and a 5.7 GHz two stage class-A CMOS PA in TSMC standard 0.18mm CMOS process. The CMOS RF receiver includes a differential LNA with gain control, an active double-balanced mixer, and an L-C tank CMOS VCO. The RF is from 5.725 to 5.825 GHz, the LO is from 5.265 to 5.325GHz and the IF is at 480 MHz. The LNA exhibits a gain of 11dB, noise figure of 4.2dB and input P1dB of –11dBm. The mixer exhibits a conversion gain of 11.06dB , noise figure of 12.8dB and input P1dB of –16.4dBm. The L-C tank CMOS VCO has an output frequency from 5099 to 5242MHz with -90.8dBc/Hz@100KHz phase noise. The VCO is used in a designed 5- GHz frequency synthesizer. The synthesizer with a spur below 58dBc has a settling time of 71.3ms for 20MHz step. The 5.7-GHz CMOS RF receiver (with the frequency synthesizer) exhibits a conversion gain of 19.1dB, noise figure of 6.6dB, input P1dB of – 30.8dBm. For the digital modulation measurement, a 5.744MHz 802.11a 18Mbps and 54Mbps OFDM signal are applied to the receiver. The measured EVM is about 2.57%(QPSK) and 1.96%(64QAM). ...展开收缩
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