VHDL时钟倍频的设计 library IEEE; Library UNISIM; use IEEE

文件名称: VHDL时钟倍频的设计

所属分类: 硬件开发

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文件大小: 2kb

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上传时间: 2009-06-04

提供者: longwi******

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详细说明： library IEEE; Library UNISIM; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use UNISIM.vcomponents.all; entity pin_test is port ( rst_manu_h :in std_logic; clk_in :in std_logic; FPGA_CR2 :out std_logic; FPGA_CR1 :out std_logic; FPGA_PR :out std_logic; FPGA_TCK :out std_logic; test_out :out std_logic; FPGA_RST :out std_logic --LED : out std_logic_vector(3 downto 0) ); end pin_test; architecture rtl of pin_test is signal clk_div1 : integer range 0 to 2086; signal clk_div : std_logic_vector(27 downto 0); signal clk_div2 : std_logic_vector(27 downto 0); signal clk0 : std_logic; signal clk180 : std_logic; signal clk_180 : std_logic; signal clk2x : std_logic; signal CLKFX : std_logic; signal clk : std_logic; signal clkdv : std_logic; signal clkin_buf : std_logic; signal clk_sys : std_logic; signal reset : std_logic; signal TX_CLK : std_logic; signal tem1: std_logic; signal tem2 : std_logic; begin clk <= clkin_buf ; reset <= not rst_manu_h; CLK_DIVIDOR1:process(clk) begin if(clk'event and clk = '1')then if clk_div1=2086 then --clk_div1 <=(others=>'0'); clk_div1 <=0; else clk_div1<= clk_div1 + 1; end if; end if; end process CLK_DIVIDOR1; CLK_DIVIDOR:process(CLKFX) begin if(CLKFX'event and CLKFX= '1') then clk_div<= clk_div + 1; end if; end process CLK_DIVIDOR; CLK_DIVIDOR2:process(CLKFX) begin if(CLKFX'event and CLKFX = '0') then clk_div2<= clk_div2 + 1; end if; end process CLK_DIVIDOR2; tem1 <='1' when clk_div1 >2068 else '0'; tem2 <= clk or tem1; test_out <= CLKFX ; FPGA_CR2 <= not tem2; FPGA_CR1 <= clk or tem1; FPGA_PR <= clk_div(15); FPGA_TCK <='1' when clk_div1 >2068 else '0'; FPGA_RST <= clk_div(0)and clk_div2(0); ----------------------------------------------------------------------- -- This section contains clock manager. ----------------------------------------------------------------------- IBUFG_clock : IBUFG generic map ( IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IOSTANDARD => "DEFAULT") port map ( O => clkin_buf, -- Clock buffer output I => clk_in -- Clock buffer input (connect directly to top-level port) ); BUFG_clk_sys : BUFG port map ( O =>clk_sys, -- Clock buffer output I => CLK0 -- Clock buffer input ); BUFG_clk_fx : BUFG port map ( O => TX_CLK, -- Clock buffer output I => CLKFX -- Clock buffer input ); DCM_gnet : DCM generic map ( CLKDV_DIVIDE => 8.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 CLKFX_MULTIPLY => 2, -- Can be any integer from 1 to 32 CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature CLKIN_PERIOD => 0.0, -- Specify period of input clock CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or -- an integer from 0 to 15 DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE FACTORY_JF => X"C080", -- FACTORY JF Values PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE port map ( CLK0 => CLK0, -- 0 degree DCM CLK ouptput -- CLK180 => CLK180, -- 180 degree DCM CLK output -- CLK270 => CLK270, -- 270 degree DCM CLK output CLK2X => CLK2X, -- 2X DCM CLK output --100MHZ -- CLK2X180 => CLK2X180, -- 2X, 180 degree DCM CLK out -- CLK90 => CLK90, -- 90 degree DCM CLK output -- CLKDV => CLKDV, -- Divided DCM CLK out (CLKDV_DIVIDE) CLKFX => CLKFX, -- DCM CLK synthesis out (M/D) -- CLKFX180 => CLKFX180, -- 180 degree CLK synthesis out -- LOCKED => LOCKED, -- DCM LOCK status output -- PSDONE => PSDONE, -- Dynamic phase adjust done output -- STATUS => STATUS, -- 8-bit DCM status bits output CLKFB => clk_sys, -- DCM clock feedback CLKIN => clkin_buf, -- Clock input (from IBUFG, BUFG or DCM) -- PSCLK => PSCLK, -- Dynamic phase adjust clock input -- PSEN => '0', -- Dynamic phase adjust enable input -- PSINCDEC => PSINCDEC, -- Dynamic phase adjust increment/decrement --RST => rst_manu_h -- DCM asynchronous reset input RST => reset -- DCM asynchronous reset input ); end rtl ...展开收缩

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