说明:`timescale 1ns / 1ps
module flow(
clk,
reset,
led
);
input clk;
input reset;
output [3:0] led;
reg [3:0] led;
reg [11:0] counter; //计数器
reg [2:0] state; //状态控制
//计数器
always (posedge clk or negedge reset)
begin
if(!reset) begin
counter <= 12'd0
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