文件名称:
Low-voltage LDO Compensation Strategy
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文件大小: 384kb
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上传时间: 2010-12-04
详细说明： In this communication, we propose a Miller compensation technique for low voltage LDO regulators which makes use of a current amplifier. The analysis shows how to design the compensation network when no voltage buffer is placed between the LDO error amplifier and power device and suggests a low supply voltage circuit topology that allows to compensate with a reasonably low integrated capacitance, to avoid oscillations due to the complex-conjugate poles at high output currents and to obtain acceptable under/overshoots during fast transient load variations. The designed LDO regulator can work with a supply voltage down to 1.2V with a drop-out voltage of 200mV at maximum load current of 100 mA; the integrated compensation capacitance is 25 pF, the load capacitor being equal to 1 μF. Simulations in good agreement with the theoretical results are also shown. ...展开收缩
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