Verilog HDL Coding The Verilog HDL coding standard

文件名称: Verilog HDL Coding

所属分类: C++

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文件大小: 466kb

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上传时间: 2011-03-03

提供者: pp***

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详细说明： The Verilog HDL coding standards pertain to Virtual Component (VC) generation and deal with naming conventions, documentation of the code and the format, or style, of the code. Conformity to these standards simplifies reuse by describing insight that is absent from the code, making the code more readable and assuring compatibility with most tools. Any exceptions to the rules specified in this standard, except as noted, must be justified and documented. The standards promote reuse by ensuring a high adaptability among application s. The intent of this document is to ensure that the gate level implementation is identical to the HDL code as it is understood by a standard Verilog simulator. Partitioning can affect the ease that a model can be adapted to an application. The modeling practices section deals with structures that are typically difficult to address well in a synthesis environment and are needed to ensure pre- and post-synthesis consistency. These standards apply to behavioral as well as synthesizable code. Additionally, these standards apply to all other code written in Verilog, such as testbenches and monitors. Some of the standards explicitly state the type of code to which they apply, and exceptions to the standards are noted. The rules were determined to be items that enable rapid SoC design, integration, and production, as well as enable maintainability by someone other than the original author. Note that in many cases, a guideline may fit this definition, however, at this point it may have a large number of exceptions, tool limitations, or a deeply entrenched opposing usage which prohibited the rule designation. ...展开收缩

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