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详细说明： This document comprises the Hardware User’s Manual for the API-FDX2-V2 PCI Card, consisting of the API-FDX2-V2 electronic module. The document covers the hardware installation, the board connections, a general description of the hardware architecture and the tec hnical data of the API-FDX2-V2. For programming information please refer to the according documents listed in the 'Applicable Documents' section. The API-FDX2-V2 module is a member of AIM's family of advanced PMC-Bus modules for analyzing, simulating, monitoring and testing of avionic databus systems. The API-FDX-2 module is used to simulate, monitor and inject protocol errors of AFDX based network systems. The API-FDX-2 offers an interface of two single or one redundant AFDX network port(s) using a half sized single card PCI bus slot of an IBM compatible PC. The on-board processing capabilities and the large memory size of the SDRAM and SSRAM enables autonomous operation with a minimal interaction of the PC host processor. A powerful PCI-Controller and Memory Arbiter is realized in a field programmable gate array. This FPGA supports both, the interface to the application and driver software tasks running on the host computer, and assists the communication for data transfer. The advanced architecture uses two processors. A powerful 64bit RISC processor (ASP) assists and supports the application and driver software tasks, and expands the capability of the API-FDX2-V2 modules to that of a high level instrument. To fulfill the real-time requirements of avionic type databus systems a high performance 32bit RISC processor (BIP) is implemented for the Bus Interface Unit (BIU). An free wheeling IRIG B Time Code Decoder is implemented on the API-FDX2-V2 boards to satisfy the requirements of 'multi-channel time tag synchronization' on system level. ...展开收缩
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