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详细说明： Introduction Point-to-point designers face many challenges when laying out a new printed circuit board (PCB). The designer may need to arrange groups of devices within a certain area of the PCB, to place components away from critical keep-out zones, include addi tional solder pads for future component upgrades, or even ensure the design is robust enough to support a potentially faster memory speed. Additional features—like test points, sockets, and alignment holes—may also be needed. Combining these requirements with an already complex PCB floor plan can make a point-to-point layout extremely difficult to complete. DDR2 SDRAM memory can make floor planning easier with the use of JEDEC-standard FBGA packages. The predefined ball out with a simple addressing scheme that supports all densities and configurations helps make it easy to design for future memory upgrades. Another layout advantage of DDR2 memory is support for on-die termination (ODT). ODT improves signal quality while eliminating most of the external parallel termination resistors. By eliminating termination resistors for memory I/O, available board space is increased and the number of through-hole vias is reduced. This document does not go into detail on PCB stack-ups, types of traces (stripline vs. microstrip), or topology characterization for the various nets. This technical note does provide general guidelines for developing the PCB floor plan, points out some of the key features of DDR2 technology, and identifies what to consider when starting a new pointto- point design that uses DDR2 SDRAM devices. A Micron DDR2 ...展开收缩
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