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上传时间: 2012-05-07
详细说明： DDR3 protocol 3 Functional Description.............................................................................................................17 3.1 Simplified State Diagram.................................................................................................17 3.2 Basic Functionality ..........................................................................................................18 3.3 RESET and Initialization Procedure ................................................................................19 3 .3.1 Power-up Initialization Sequence .............................................................................19 3.3.2 Reset Initialization with Stable Power......................................................................21 3.4 Register Definition...........................................................................................................22 3.4.1 Programming the Mode Registers ............................................................................22 3.4.2 Mode Register MR0..................................................................................................23 3.4.3 Mode Register MR1..................................................................................................27 3.4.4 Mode Register MR2..................................................................................................30 3.4.5 Mode Register MR3..................................................................................................32 4 DDR3 SDRAM Command Description and Operation...........................................................33 4.1 Command Truth Table .....................................................................................................33 4.2 CKE Truth Table..............................................................................................................35 4.3 No OPeration (NOP) Command ......................................................................................36 4.4 Deselect Command ..........................................................................................................36 4.5 DLL-off Mode..................................................................................................................37 4.6 DLL on/off switching procedure......................................................................................38 4.6.1 DLL “on” to DLL “off” Procedure...........................................................................38 4.6.2 DLL “off” to DLL “on” Procedure...........................................................................39 4.7 Input clock frequency change ..........................................................................................40 4.8 Write Leveling .................................................................................................................42 4.8.1 DRAM setting for write leveling & DRAM termination function in that mode ......43 4.8.2 Procedure Description...............................................................................................43 4.8.3 Write Leveling Mode Exit .............................. ...展开收缩
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