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上传时间: 2012-06-26
详细说明： 1 1 1 PRODUCT OVERVIEW 1.1 FEATURES Memory configuration Two 8-bit Timer/Counter ROM size: 1K * 16 bits. One 8-bit timer with external event counter, RAM size: 64 * 8 bits. Buzzer0 and PWM0. (TC0). One 8-bit timer with external event counter, 4 levels stack buffer. Buzzer1 and PWM1. (TC1). 5 interrupt sources 5+1 channel 12-bit SAR ADC. 3 internal interrupts: TC0, TC1, ADC Five external ADC input 2 external interrupt: INT0, INT1 One internal battery measurement Internal AD reference voltage (VDD, 4V, 3V, 2V). I/O pin configuration Bi-directional: P0, P4, P5. On chip watchdog timer and clock source is Input only: P0.4. Internal low clock RC type (16KHz(3V), 32KHz Pull-up resisters: P0, P4, P5. Wakeup: P0 level change. 4 system clocks ADC input pin: P4.0~P4.4. External high clock: RC type up to 10 MHz External Interrupt trigger edge: External high clock: Crystal type up to 16 MHz P0.0 controlled by PEDGE register. Internal high clock: 16MHz RC type P0.1 is falling edge trigger only. Internal low clock: RC type 16KHz(3V), 32KHz(5V 3-Level LVD 4 operating modes Reset system and power monitor. Normal mode: Both high and low clock active Slow mode: Low clock only. Powerful instructions Sleep mode: Both high and low clock stop Instruction‟s length is one word. Green mode: Periodical wakeup by TC0 timer Most of instructions are one cycle only. All ROM area JMP/CALL instruction. Package (Chip form support) All ROM area lookup table function (MOVC). DIP 14 pin SOP 14 pin Fcpu (Instruction cycle) SSOP 16 pin Fcpu = Fosc/1, Fosc/2, Fosc/4, Fosc/8, Fosc/16, ...展开收缩
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