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详细说明： FPGA 控制 LCD 1602调试笔记 初始化步骤： 1、0x38 设置为16*2显示，5*7点阵，8位数据接口 2、0x0C 说明 这里0c表示的是开显示，不显示光标，光标不显示，完整描述如下： 3、0x01 清屏幕 4、0x06 表示读或者写之后，地址指针加1，光标加1 5、0x80 位置寄存器定位于第一行的最左边 时序图： 在本例中采用50兆分频到1k的时钟，也就是E的保持时间是1ms，达到以上的时序要求。 在Altera的DEO上验证通过，显示效果如下： 完整代码如下： （本实例中，显示大写的LOVE!,第二行显示www.txsky.net） module lcm(LCD_ON, CLOCK_50, LCD_DATA, LCD_RW, LCD_RS, LCD_EN, LCD_BLON ); input CLOCK_50; output [7:0]LCD_DATA; output LCD_RW; output LCD_RS; output LCD_EN; output LCD_BLON; output LCD_ON; reg [7:0]LCD_DATA; reg LCD_RW ; reg LCD_ RS; reg LCD_EN; reg clk_1k=1'b0; reg [20:0]counter=0; reg [10:0]counter1=0; assign LCD_BLON=1;//这里要么不设置数据类型，要么设置为wire assign LCD_ON=1;// 这里要么不设置数据类型，要么设置为wire always@(posedge CLOCK_50) if(counter==25000) begin clk_1k<=~clk_1k; counter<=0; end else counter<=counter+1; always@(posedge clk_1k)// //很巧妙的利用时钟来解决延时问题，特别是在时序电路的//时候 begin if(counter1<1023)//这里counter1没有给定它为0的条件，及counter1是一次性 counter1<=counter1+1;//执行的。当counter1超过1023这个值时counter1保持不变//这样下面要显示的数就会保持稳定。 casex (counter1) 400:begin LCD_DATA<=8'b00111000; //0x38 设置显示模式 LCD_RW<=1'b0; LCD_RS<=1'b0; end 401:LCD_EN<=1'b1; 410: //0x0c 开显示 关光标 begin LCD_DATA<=8'b00001100; LCD_RW<=1'b0; LCD_RS<=1'b0; end 411: LCD_EN<=1'b1; 420: begin //0x01 清屏幕 LCD_DATA<=8'b00000001; LCD_RW<=1'b0; LCD_RS<=1'b0; end 421: LCD_EN<=1'b1; 430: begin //0x06 读或者写后 自动加1 LCD_DATA<=8'b00000110; LCD_RW<=1'b0; LCD_RS<=1'b0; end 431: LCD_EN<=1'b1; 440:begin //0xc0 定位到第二行 LCD_DATA<=8'b11000000; LCD_RW<=1'b0; LCD_RS<=1'b0; end 441: begin LCD_EN<=1'b1; ack<=1;//这里是多余的， end 450: begin //write data W LCD_DATA<=8'h57; LCD_RW<=1'b0; LCD_RS<=1'b1; end 451: LCD_EN<=1'b1; 460: begin //write data W LCD_DATA<=8'h57; LCD_RW<=1'b0; LCD_RS<=1'b1; end 461: LCD_EN<=1'b1; 470: begin //write data W LCD_DATA<=8'h57; LCD_RW<=1'b0; LCD_RS<=1'b1; end 471: LCD_EN<=1'b1; 480: begin //write data . LCD_DATA<=8'h2E; LCD_RW<=1'b0; LCD_RS<=1'b1; end 481: LCD_EN<=1'b1; 490: begin //write data T LCD_DATA<=8'h54; LCD_RW<=1'b0; LCD_RS<=1'b1; end 491: LCD_EN<=1'b1; 500:begin //write data X LCD_DATA<=8'h58; LCD_RW<=1'b0; LCD_RS<=1'b1; end 501: LCD_EN<=1'b1; 510:begin //write data S LCD_DATA<=8'h53; LCD_RW<=1'b0; LCD_RS<=1'b1; end 511: LCD_EN<=1'b1; 520: begin //write data K LCD_DATA<=8'h4B; LCD_RW<=1'b0; LCD_RS<=1'b1; end 521: LCD_EN<=1'b1; 530: begin //write data Y LCD_DATA<=8'h59; LCD_RW<=1'b0; LCD_RS<=1'b1; end 531: LCD_EN<=1'b1; 540: begin //write data . LCD_DATA<=8'h2E; LCD_RW<=1'b0; LCD_RS<=1'b1; end 541: LCD_EN<=1'b1; 550: begin //write data N LCD_DATA<=8'h4E; LCD_RW<=1'b0; LCD_RS<=1'b1; end 551: LCD_EN<=1'b1; 560: begin //write data E LCD_DATA<=8'h45; LCD_RW<=1'b0; LCD_RS<=1'b1; end 561: LCD_EN<=1'b1; 570: begin //write data T LCD_DATA<=8'h54; LCD_RW<=1'b0; LCD_RS<=1'b1; end 571: LCD_EN<=1'b1; 580: begin //定位到第一行 LCD_DATA<=8'h80; LCD_RW<=1'b0; LCD_RS<=1'b0; end 581: LCD_EN<=1'b1; 590: begin //write data L LCD_DATA<=8'h4C; LCD_RW<=1'b0; LCD_RS<=1'b1; end 591: LCD_EN<=1'b1; 600: begin //write data O LCD_DATA<=8'h4F; LCD_RW<=1'b0; LCD_RS<=1'b1; end 601: LCD_EN<=1'b1; 610: begin //write data V LCD_DATA<=8'h56; LCD_RW<=1'b0; LCD_RS<=1'b1; end 611: LCD_EN<=1'b1; 620: begin //write data E LCD_DATA<=8'h45; LCD_RW<=1'b0; LCD_RS<=1'b1; end 621: LCD_EN<=1'b1; 630: begin //write data ! LCD_DATA<=8'h21; LCD_RW<=1'b0; LCD_RS<=1'b1; end 631: LCD_EN<=1'b1; default: LCD_EN<=1'b0; endcase end endmodule ...展开收缩
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