文件名称:
Configuration and Readback of Virtex FPGAs Using JTAG Boundary-Scan
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文件大小: 359kb
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上传时间: 2012-11-21
详细说明： The IEEE 1149.1 Test Access Port (TAP) and Boundary-Scan architecture, commonly referred to as JTAG, is a popular testing method. JTAG is an acronym for the Joint Test Action Group, the technical subcommittee initially responsible for developing the standard. This standard provides a means to ensure the integrity ofindividual board-level components and their interconnections. With increasingly dense multi-layer PC boards and more sophisticated surface mounting techniques, Boundary-Scan testing is becoming widely used a s an important debugging standard. Devices containing Boundary-Scan logic can send data out on I/O pins in order to test connections between devices at the board level. The circuitry can also be used to send signals internally to test the device specific behavior.These tests are commonly used to detect opens and shorts at both the board and device level. In addition to testing, Boundary-Scan offers the flexibility for a device to have its own set of user-defined instructions. The added common vendor-specific instructions, such as configure and verify, have increased the popularity ofBoundary-Scan testing and functionality. ...展开收缩
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