文件名称:
Fujitsu MB86H61 Device Manual
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文件大小: 11mb
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上传时间: 2013-07-22
详细说明： The MB86H61 is a highly integrated HD Multi-Standard Digital Television Decoder designed to meet the needs of tomorrow’s HD set-top-box and IDTV market featuring CI+ or embedded CAS for advanced security. The MB86H61 is a single-chip video decoder supporting H.264 / AVC, MPEG-2, AVS and VC-1 video decoding up to high definition resolution with up to 1080p 50/60Hz output. A high performance ARM 1176JZF-STM CPU with more than 475DMIPS, a 16kB data and instruction caches and TCM is included. The CPU features an integrated memory ma nagement unit and a floating point co-processor. The chip uses two DDR2 interfaces in shared memory architecture. Also integrated is a 2D graphic engine to accelerate OSD. An advanced, programmable audio processor solution offers full flexibility. It is capable of decoding MPEG1 layer 1, 2 and 3 (MP3), HE-AAC, Dolby Digital (planning) and Dolby Digital plus (planning). Available audio outputs are 4x I²S from 8kHz to 192kHz, SPDIF and stereo audio DAC. The TV or display can be connected in HD resolution analog via component output or digital via copy protected HDMI interface. A down-sampled SD format can be provided in parallel. Additionally the decoded video can be output via CCIR656 (SD) or SMPTE 296M/274M (HD). The MB86H61 supports eSATA/SATA 3Gb/s interface for external hard disk drives and SDIO e.g. for SDHC memory cards. Two USB 2.0 ports configurable as host or device and 10/100 Base-T Ethernet MAC are provided for connectivity. A deep power down mode has been added to allow a system design with very low power consumption during standby mode. The MB86H61 comes with the Fujitsu Driver Application Programming Interface (FAPI) to help customers achieving the shortest possible development cycle. FAPI is a complete driver set allowing fast and efficient customer software design. ...展开收缩
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