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详细说明： PCI9054的英文版本数据手册 PCI Specification version 2.2 (v2.2) compliant 32-bit, 33-MHz Bus Master Interface Controller with PCI Power Management features for adapters and embedded systems • General Purpose Bus Master Interface featuring advanced Data Pipe Architecture™ technology, which includes two DMA engines, programmable Target and Initiator Data Transfer modes and PCI messaging functions • PCI v2.2 Vital Product Data (VPD) configuration support • PCI Dual Address Cycle (DAC) support • PCI Hot Plug and CompactPCI Hot Swap compliant • I2O™ v1.5-Ready Messaging Unit • Two independent DMA channels for Local Bus memory to and from PCI Host Bus Data transfers • Supports Type 0 and Type 1 Configuration cycles • Programmable Burst Management • Programmable Interrupt Generator • Six programmable FIFOs for zero wait state burst operation • PCI ↔ Local Data transfers up to 132 MB/s • 3.3V, 5V tolerant PCI and Local signaling supports Universal PCI Adapter designs, 3.3V core, lowpower CMOS in 176-pin PQFP and 225-pin PBGA • Supports Local Bus Direct-Connect to the Motorola MPC850 or MPC860 PowerQUICC™, Intel i960 family and IBM PPC401 CPUs and similar bus protocol devices • Programmable Local Bus runs up to 50 MHz and supports non-multiplexed 32-bit address/data, multiplexed 32-bit, and slave accesses of 8-, 16-, or 32-bit Local Bus devices • Serial EEPROM interface • Three PCI-to-Local Address spaces • Programmable Local Bus wait states • Programmable prefetch counter • Local Bus runs asynchronously to the PCI Bus • Eight 32-bit Mailbox and two 32-bit Doorbell registers • Performs Big Endian ↔ Little Endian conversion • PCI-to-Local Delayed Read mode • Local-to-PCI Deferred Read mode (M mode only) • Flexible 3.3V, 5V Tolerant Local Bus operation up to 50 MHz • Industrial Temp Range operation Figure 1-1. Typical Adapter Block Diagram PC ...展开收缩
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