文件名称:
Static Timing Analysis in VLSI Design.pdf
开发工具:
文件大小: 3mb
下载次数: 0
上传时间: 2019-05-23
详细说明： iming,timing,timing!Thatisthemainconcernofadigitaldesigner chargedwithdesigningasemiconductorchip.Whatisit,howisit described,andhowdoesoneverifyit?Thedesignteamofalarge digitaldesignmayspendmonthsarchitectinganditeratingthedesignto achievetherequiredtimingtarget.Besidesfunctionalverification,thetim- ingclosureisthemajormilestonewhic hdictateswhenachipcanbere- leasedtothesemiconductorfoundryforfabrication.Thisbookaddresses thetimingverificationusingstatictiminganalysisfornanometerdesigns. Thebookhasoriginatedfrommanyyearsofourworkingintheareaof timingverificationforcomplexnanometerdesigns.Wehavecomeacross manydesignengineerstryingtolearnthebackgroundandvariousaspects ofstatictiminganalysis.Unfortunately,thereisnobookcurrentlyavail- ablethatcanbeusedbyaworkingengineertogetacquaintedwiththede- tailsofstatictiminganalysis.Thechipdesignerslackacentralreferencefor informationontiming,thatcoversthebasicstotheadvancedtimingverifi- cationproceduresandtechniques. Thepurposeofthisbookistoprovideareferenceforbothbeginnersas wellasprofessionalsworkingintheareaofstatictiminganalysis.Thebook T PREFACE xvi isintendedtoprovideablendoftheunderlyingtheoreticalbackgroundas wellasin-depthcoverageoftimingverificationusingstatictiminganaly- sis.Thebookcoverstopicssuchascelltiming,interconnect,timingcalcula- tion,andcrosstalk,whichcanimpactthetimingofananometerdesign.It describeshowthetiminginformationisstoredincelllibrarieswhichare usedbysynthesistoolsandstatictiminganalysistoolstocomputeandver- ifytiming. ThisbookcoversCMOSlogicgates,celllibrary,timingarcs,waveform slew,cellcapacitance,timingmodeling,interconnectparasiticsandcou- pling,pre-layoutandpost-layoutinterconnectmodeling,delaycalculation, specificationoftimingconstraintsforanalysisofinternalpathsaswellas IOinterfaces.Advancedmodelingconceptssuchascompositecurrent source(CCS)timingandnoisemodels,powermodelingincludingactive andleakagepower,andcrosstalkeffectsontimingandnoisearedescribed. Thestatictiminganalysistopicscoveredstartwithverificationofsimple blocksparticularlyusefulforabeginnertothisarea.Thetopicsthenextend tocomplexnanometerdesignswithconceptssuchasmodelingofon-chip variations,clockgating,half-cycleandmulticyclepaths,falsepaths,aswell astimingofsourcesynchronousIOinterfacessuchasforDDRmemoryin- terfaces.Timinganalysesatvariousprocess,environmentandinterconnect cornersareexplainedindetail.Usageofhierarchicaldesignmethodology involvingtimingverificationoffullchipandhierarchicalbuildingblocksis coveredindetail.Thebookprovidesdetaileddescriptionsforsettingup thetiminganalysisenvironmentandforperformingthetiminganalysisfor variouscases.Itdescribesindetailhowthetimingchecksareperformed andprovidesseveralcommonlyusedexamplescenariosthathelpillustrate theconcepts.Multi-modemulti-corneranalysis,powermanagement,as wellasstatisticaltiminganalysesarealsodescribed. Severalchaptersonbackgroundreferencematerialsareincludedintheap- pendices.TheseappendicesprovidecompletecoverageofSDC,SDFand SPEFformats.Thebookdescribeshowtheseformatsareusedtoprovide informationforstatictiminganalysis.TheSDFprovidescellandintercon- nectdelaysforadesignunderanalysis.TheSPEFprovidesparasiticinfor- mation,whicharetheresistanceandcapacitancenetworksofnetsina PREFACE xvii design.BothSDFandSPEFareindustrystandardsandaredescribedinde- tail.TheSDCformatisusedtoprovidethetimingspecificationsorcon- straintsforthedesignunderanalysis.Thisincludesspecificationofthe environmentunderwhichtheanalysismusttakeplace.TheSDCformatis adefactoindustrystandardusedfordescribingtimingspecifications. Thebookistargetedforprofessionalsworkingintheareaofchipdesign, timingverificationofASICsandalsoforgraduatestudentsspecializingin logicandchipdesign.Professionalswhoarebeginningtousestatictiming analysisorarealreadywell-versedinstatictiminganalysiscanusethis booksincethetopicscoveredinthebookspanawiderange.Thisbook aimstoprovideaccesstotopicsthatrelatetotiminganalysis,witheasy-to- readexplanationsandfiguresalongwithdetailedtimingreports. Thebookcanbeusedasareferenceforagraduatecourseinchipdesign andasatextforacourseintimingverificationtargetedtoworkingengi- neers.Thebookassumesthatthereaderhasabackgroundknowledgeof digitallogicdesign.Itcanbeusedasasecondarytextforadigitallogicde- signcoursewherestudentslearnthefundamentalsofstatictiminganalysis andapplyitforanylogicdesigncoveredinthecourse. Ourbookemphasizespracticalityandthoroughexplanationofallbasic conceptswhichwebelieveisthefoundationoflearningmorecomplextop- ics.Itprovidesablendoftheoreticalbackgroundandhands-onguideto statictiminganalysisillustratedwithactualdesignexamplesrelevantfor nanometerapplications.Thus,thisbookisintendedtofillavoidinthis areaforworkingengineersandgraduatestudents. ThebookdescribestimingforCMOSdigitaldesigns,primarilysynchro- nous;however,theprinciplesareapplicabletootherrelateddesignstyles aswell,suchasforFPGAsandforasynchronousdesigns.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
相关说明
- 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
- 本站是交换下载平台，提供交流渠道，下载内容来自于网络，除下载问题外，其它问题请自行百度。
- 本站已设置防盗链，请勿用迅雷、QQ旋风等多线程下载软件下载资源，下载后用WinRAR最新版进行解压.
- 如果您发现内容无法下载，请稍后再次尝试；或者到消费记录里找到下载记录反馈给我们.
- 下载后发现下载的内容跟说明不相乎，请到消费记录里找到下载记录反馈给我们，经确认后退回积分.
- 如下载前有疑问，可以通过点击"提供者"的名字，查看对方的联系方式，联系对方咨询.
相关搜索:
