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IHI0068C_low_power_interface_spec.pdf
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aRM contract rcfcrenccs: LES-PRE-20414 ARM LOW POWER INTERFACE SPECIFICATION LICENCE
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ARM IHI 0068C
Copyright 2013, 2014, 2016 ARM Limited or its affiliates. A rights reserved
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ARM IHI 0068C
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Contents
AMBA Low Power Interface Specification ARM
Q-Channel and P-Channel Interfaces
Chapter 1
Introduction
About the low-power interfaces
1-8
Interface differences and selection
19
Chapter 2
Interface Specification
Q-Channel interface specification
2-12
2.2
P-Channel interface specification
2-19
Chapter 3
Implementation Guidelines
Q-Channel implementation
3.2 P-Channel implementation.....
3-3
Chapter 4
Application Examples
1 Q-Channel application examples
4.2
P-Channel application examples
4-37
Chapter 5
Q-Channel Backward Compatibility
Q-Channel backwards compatibility
5-42
Appendix A
Revisions
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Chapter 1
Introduction
The following sections introduce the low-power interfaces, and describe the differences between them
About the low-power interfaces on pagc 1-8
Interface differences and selection on page 1-9
ARM|H|0068
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1 Introductian
1. 1 About the low-power interfaces
1.1 About the low-power interfaces
This document dcscribcs interfaces that can bc uscd to control the clock and powcr statcs of dcviccs. Thc interfaces
Q-Channel Intended for use where simple run-stop quiescence semantics are suitable. Q-Channel is an
cvolution of thc AXI low-powcr intcrfacc, and its naming reflects the fact that the purposc of thc
interface is the control of device quiescence
P-Channel Intended for management of complex power scenarios with multiple transitions. These transitions
can be made without returning the device to a
able state. Its nar
eflects the fact
that the purpose of the interface is the control of power state transitions
1.1.1 Common characteristics
Thc Q-Channcl and P-Channcl interfaces havc the following common charactcristics
Controller-managed transitions between device states
a device can
Indicate that it must exit a lo
state and enter a higher-functioning
Hint that it might accept a request to enter a lower-power state
Optionally, a devicc can dcny a statc changc rcqucst
Clock domain crossing semantics are robust, to support asynchronous interfacing
There arc no restrictions on the spccific charactcristics of the states that the interfaces manage
18
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1 introduction
1.2/nterface differences and selection
1.2
Interface differences and selection
ARM intends the two interfaces to complement cach othcr, and that the interfaces arc uscd as circumstanccs dictate
The simple run-stop quiescence semantics of Q-Channel are ideal for clock control or simple power contro
scenarios. Thc quiescent statc cntcrcd can vary, but only according to thc common configuration of both the devicc
and controller before entering the quiescent state. The quiescent state exit transition is always to a common operable
running state. This must be entered before the device can enter a different quiescent state
P-Channel can handle more complex scenarios. Multiple transitions can be made without returning the device,or
device partition, to a common operable state between successive power-saving states. The controller provides an
explicit state request at each transition, so common configuration of the controller and device is not needed
Typically, each P-Channel maps directly from a controller to the management of a power domain partition of a
singlc devicc. The P-Channcl interface is uscd only if Q-Channcl functionality is insufficient.
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1 Introductio
1.2 Interface differences and selection
1-10
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