57850.pdf（HT12D说明书）HT12D的说明书，非常好用，非常利于大学生或者在职员工进行研

文件名称: 57850.pdf（HT12D说明书）

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上传时间: 2019-07-14

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详细说明：HT12D的说明书，非常好用，非常利于大学生或者在职员工进行研究工作，非常详尽地描述了HT12D地用法和特性，以及一些用法和应有范围和注意事项H口LTEK HT12D/HT12F Block Diagram OSC2 OSC1 Oscillator Divider Register, Latch Circuit iData DIN O Buffer Data detector Sync Detector comparator Comparator Control Logic Transmission gate circuit Buffer VDD VSS Note: The address/data pins are available in various combinations(see the address/data table) Pin Assignment 8-Address 8∽ Address 12-Address 12-Address 4-Data 4-Data 0-Data 0-Data NC口1 20口Nc 20□NC A0口1 18 □VDD A0囗2 19口VDD A01 18BVDD A0囗2 19□VDD 17DVT 18口VT A1囗2 17□vT A1口3 18口VT 16日05c1A2口4 17BOSC1 A2[ 3 16口osc1A2口4 17口sc1 A3口4 15日osc2A3日5 6口oSc2A3囗4 15 F OSC2 A3 5 16日osc2 A4囗5 14口DN A4口6 15口D|N A4囗5 14□D|N A4日6 15口D|N A5囗6 13□D11 A5囗7 14口D11 A56 13□A11 A5囗7 14口A11 6匚 2D10A6口8 13口D10 2A10A6口8 13口A10 A78 A7口9 12口D A7口8 11{A9 A7口9 12□A9 Vss凵9 10BD8 VSS d 10 11□D VSS囗9 10凵A8 VSS囗10 HT12D HT12F HT12F 18 DIPA 20 SOP-A 18 DIP-A 20 SOP-A Pin Description Pin na Connecti Description A0~A11(HT12F) Input pins for address A0-A11 setting MOS These pins can be externally set to Vss or left open A0-A7(HT12D) Transmission Gate Input pins for address A0-A7 setting Thes externally set to VsS D8-D11(HT12D)0 CMOS OUT Output data pins, power-on state is low. DIN CMOS Serial data input pin VT CMOS OUT Valid transmission, active high OSC1 Oscillator Oscillator input pin Oscillator Oscillator output pin VSS Negative power supply, ground VDD Positive power supply Rev.1.10 November 18. 2002 H口LTEK HT12D/HT12F Approximate internal connection circuits Transmission Gate CMOS OUT CMOS IN Oscillator Absolute Maximum Ratings Supply Voltage 0.3V to 13V Storage Temperature 50°to125°C Input Voltage Vss-0.3 to VDD+0. 3v Operating Temperature 20°cto75° Note: These are stress ratings only. Stresses exceeding the range specified under"Absolute Maximum Ratings"may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil Electrical characteristics Ta=25C Test Conditions Symbol Parameter Min.Typ.Max.Unit DD Conditions Operating Voltage 24 12 V 5V 0 A STB Standby current Oscillator stops 12V 4 Operating Current 5V No load, fosc=150kHz 200400u Data Output Source Current(D8-D11)5V VOH=4.5V 1.6 mA Data Output Sink Current(D8-D11) 5V VOL=0.5V 1.6 mA VT Output Source Current VOH=4.5V 1.6 mA VT VT Output Sink Current 5NJN0=0.5V 1.6 mA H HInput voltage 5V V "L Input Voltage 5V 0 Oscillator Frequency 5V Rosc=51kS2 150 KHz Rev.1.10 November 18. 2002 H口LTEK HT12D/HT12F Functional Description Flowchart The 2 series of decoders provides various combina The oscillator is disabled in the standby state and acti- tions of addresses and data pins in different packages vated when a logic"high" signal applies to the din pin so as to pair with the 2series of encoders That is to say, the din should be kept low if there is no The decoders receive data that are transmitted by ar signal input encoder and interpret the first n bits of code period Power on addresses and the last 12-n bits as data where n is the address code number. a signal on the DIN pin activates the oscillator which in turn decodes the incoming ad Standby mode dress and data. the decoders will then check the re ceived address three times continuously If the received vt address codes all match the contents of the decoders Code in DoSa the i rest of local address the 12-n bits of data are decoded to acti- this word vate the output pins and the vt pin is set high to indicate a valid transmission. this will last unless the address code is incorrect or no signal is received Address bits matched The output of the VT pin is high only when the transmis sion is valid. Otherwise it is always low Yes Output type Store data Of the 2 series of decoders the ht 12f has no data output pin but its vT pin can be used as a momentary Match data output. The HT 12D, on the other hand, provides 4 previous stored data atch type data pins whose data remain unchanged until new data are received Part Data Address Output Operating No. Pins Pins Type Voltage of checking completed HT12D 4 8 Latch2.4V-12V Yes HT12F 0 12 2.4V~12V Latch data to output& activate vt No Address or data error YO Decoder timing Encoder Transmission Enable →<1word Encod DOU 斗 -|2“ clocks -2“coks Decoder vt H check H check Latched Rev.1.10 November 18. 2002 H口LTEK HT12D/HT12F Encoder/Decoder cross reference table Package Decoders Part no Data Pins Address Pins Decoder DIP SOP DIP SOP HT12A HT12D 8 18 HT12E 0 18 0 HT12A HT12F 0 18 HT12E 18 Address/Data sequence The following table provides address/data sequence for various models of the 2series of decoders Address/Data Bits Part No 0 8 10 T AO A A3A4 A7 D9D10D11 HT12F A1 A3 A4 A6A7 A9A10A11 Oscillator frequency vs supply voltage R。sc( 4.00 27kg2 3.50 30kg2 33k2 3.00 36k0 39kQ2 2.50 47k 51kg2 2.00 56kQ 150 82kQ 100kg2 120kQ (100kHz)100 0.50 0.25 910111213VDDⅣDc) Note: The recommended oscillator frequency is fosco(decoder)=50 foscE(HT12E encoder) E fOsCE(HT12A encoder) Rev.1.10 November 18. 2002 H口LTEK HT12D/HT12F Application Circuits Receiver Circuit Receiver Circuit ○V 18 VDD AO VDD A1 A1 OSC1 OSC116 OSC2 15 ROSC OSC2/15 Rosc DIN A4 DIN D11 A5 A1/13 D10 A10 D9 10 10 HT12D HT12F Rev.1.10 November 18. 2002 H口LTEK HT12D/HT12F Package Information 18-pin DiP (300mil outline dimensions H Dimensions in mil Min Nom 895 915 240 260 ABCDEFGH 125 135 125 145 20 50 295 315 335 375 0 15 Rev.1.10 7 November 18. 2002 H口LTEK HT12D/HT12F 20-pin SoP (300mil)outline dimensions 20 B Dimensions in mil Symbol Min N om 394 419 290 510 92 104 F 4 12 C Rev.1.10 8 November 18. 2002 H口LTEK HT12D/HT12F Product Tape and Reel specifications Reel dimensions C SOP 20W Symbol Description Dimensions in mm A Reel Outer diameter 330±1.0 B Reel Inner Diameter 62±1.5 13.0+0.5 Spindle hole diameter 0.2 D Key slit Width 2.0±05 24.8+0.3 Space Between Flange 0.2 Reel Thickness 30.2±0.2 Rev.1.10 November 18. 2002

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