DDR3L_device_operation_timing_diagram_computing.pd

文件名称: DDR3L_device_operation_timing_diagram_computing.pdf

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上传时间: 2019-07-16

提供者: wmj***

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详细说明：该文档主要讲解了DDR3/DDR3L的各种控制命令时序，以及读写操作各信号之间的关系，对理解DDR3的应用有很大的帮做。SK hynix SK hynix SK hynix plied Power Reset S,MPR) Procedure -(Initialization Write Self Refresh SRE ZQCL from any RESET state ZQCLZQC5 REF Calibrati Idle PDX Precharge Power Activating Power PDE Bank Active WRITE WRITE READ READ WRITE A READ A Writing READ Reading ARITE A READ A WRITE A READ A PRE PREA Automatic Command SK hynix SK hynix SK hynix Tc T Tf tCKSRX VDD,CdOm kE mva whot i aoytutur ivi iV iv v aD(a tDLLK VRD MOD tZQinit NTfummmRemfurmdp wae xx mo x d w e me lUHHm HHD XIA Ilmmylmmmmum Static LOW in case RTT_Nom is enabled at time Tg, otherwise sta ic HIGH o? -OW 人LD NOTE 1. From time pcint"Td"until"Tk"NOP of DES commands must be applied between MRS and ZQCL commands TIME BREAK DONT CARE SK hynix Ti CK. CK# tCKSRX DD, VDDQ RESET# CKE tOLL tURD MRD tzQinit MH3 or tumtammaaT 7: Static LOw in case RTT Norm is enabled at time Tg, otherwise static HIG or LOV/ )) ) NOTE 1. From time point"Td"until"Tk"NoP or des commands must be applied between mRS and ZQ CL command TIME BREAK D○N" T CARE SK hynix oc⑦MM贴 Z NCPIDES X IHID VALID XUITIX VALID des X VaLD IIT VALID XIN VALD C ZX vALD II VALD XT ALD YI VALD IHI VALD XZK VALID THIIX VALD XILTX VALD XL CId Settings New Settings IMOD RTT Nom ENABLED prior and/or after MRS command 02T A VALID XIX VALID A ⊥mmAD RTT_Nom DISAELED Prior and after MRS command 0u0DWw地 vai m illl X vaiin XLIL vAin Xili vain XIll vaD XUiALX VALID X!A VALD XUllIl vaLID差 Time Break 点ddre VALID UIIX VALID LIX VALID C ALID XILILX VALIC ILX VALID XILLIX VALD XILIX VALID XZLTX VALID XIIIIX VALD LX VALID XI sc:tir gs Updating Settings New Settings FTT_ Nom ENABLED prior and/or after MRS command 2 VALID XIIIXVALID XIA ATUX VAUD X RTT_Nom DISABLED prior and after MRS command or 2 VALDIX VALD X VALD D VA D XUlIX VaLc IllX NALD XIMIX VALD XIMIX VALID X VA D MIX VALD XIM VALD L VDon't

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