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00002340-RTL8881AM-CG_Datasheet_Draft-0.3_20131020_21667(For HVL).pdf
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上传时间: 2019-07-26
详细说明： RTL8881AM datasheet 5.1. PACKAGE IDENTIFICATION...........................................................................................................................................6 6. PIN DESCRIPTIONS............................................................................................................................... ..........................6 6.1. CONFIGURATION UPON POWER ON STRAPPING ...........................................................................................................9 6.2. SHARED I/O PIN MAPPING (DRQFN-164) .................................................................................................................11 6.3. GMAC PIN MODE DESCRIPTION ...............................................................................................................................13 6.3.1. MAC Interface MII/GMII/RGMII Mode Pin Sharing Mappings ..........................................................................13 6.3.2. GMII/RGMII Interface Pin Descriptions..............................................................................................................13 6.3.3. MII MAC Mode Interface Pin Descriptions .........................................................................................................14 6.3.4. MII PHY Mode Interface Pin Descriptions ..........................................................................................................14 7. MEMORY CONTROLLER............................................................................................................................................15 7.1. SDR DRAM CONTROL INTERFACE ...........................................................................................................................15 7.1.1. Features................................................................................................................................................................15 7.1.2. Bank2 and Bank3..................................................................................................................................................15 7.2. DDR DRAM CONTROLLER .......................................................................................................................................16 7.2.1. Features................................................................................................................................................................16 7.3. SPI FLASH CONTROLLER ...........................................................................................................................................16 7.3.1. Features................................................................................................................................................................16 7.3.2. Pin Mode and Definition of Serial and Dual I/O..................................................................................................16 7.4. SOFTWARE REGISTER DEFINITIONS ...........................................................................................................................17 7.4.1. Memory Control Register (MCR) (0xB800_1000) ...............................................................................................17 7.4.2. DRAM Configuration Register (DCR) (0xB800_1004)........................................................................................18 7.4.3. DRAM Timing Register (DTR) (0xB800_1008)....................................................................................................20 7.4.4. DDR DRAM Calibration Register (DDCR) (0xB800_1050)................................................................................22 7.4.5. SPI Flash Configuration Register (SFCR) (0xB800_1200)..................................................................................23 7.4.6. SPI Flash Configuration Register 2 (SFCR2) (0xB800_1204).............................................................................23 7.4.7. SPI Flash Control & Status Register (SFCSR) (0xB800_1208) ...........................................................................24 7.4.8. SPI Flash Data Register (SFDR) (0xB800_120C) ...............................................................................................25 7.4.9. SPI Flash Data Register 2 (SFDR2) (0xB800_1210)...........................................................................................25 8. PERIPHERAL AND MISC CONTROLS......................................................................................................................26 8.1. INTERRUPT CONTROL REGISTERS ..............................................................................................................................26 8.1.1. Global Interrupt Mask Register (GIMR) (0x B800_3000) ...................................................................................26 8.1.2. Global Interrupt Status Register (GISR) (0x B800_3004)....................................................................................28 8.1.3. Interrupt Routing Register 0 (IRR0) (0xB800_3008) ...........................................................................................29 8.1.4. Interrupt Routing Register 1 (IRR1) (0xB800_300C)...........................................................................................29 8.1.5. Interrupt Routing Register 2 (IRR2) (0xB800_3010) ...........................................................................................29 8.1.6. Interrupt Routing Register 3 (IRR3) (0xB800_3014) ...........................................................................................30 8.1.7. Global Interrupt Mask Register 2 (GIMR2) (0xb800-3020).................................................................................30 8.1.8. Global Interrupt Status Register 2(GISR2) (0xB800-3024) .................................................................................31 8.1.9. Interrupt Routing Register 4 (IRR4) (0xB800-3028)............................................................................................32
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