IMX8QPAEC.pdfiMX8QP数据手册，给大家分享一下，多核异构，算力超群！Introduc

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详细说明：iMX8QP数据手册，给大家分享一下，多核异构，算力超群！Introduction Table 1.i. MX 8Quad Plus advanced features (continued) Function Feature Display controller Supports single UltraHD 4kp60 display or up to 4 independent FulIHD 1080p60 displays Up to 18-layer composition Complementary 2D blitting engines and online warping functionality Integrated Failover Path (SafeAssure)to ensure display content stays valid even in event of a software failure Display l/o 2x MIPI-DSI with 4 lanes each 1x HDMl-TX/Display Port compliant wi HDM eDP 1.4 ·DP1.3 2x LVDS TX With 2 channels of 4 lanes each Camera l/o and video 2x MIPI-CSI with 4-lanes each Securit Advanced High Assurance Boot(AHAB )secure encrypted boot Random Number Generator with a high-quality entropy source generator and Hash dRBG(based on hash functions) RSA up to 4096, Elliptic Curve up to 1023 AES-128/192/256,DES,3DES,MD5,SHA-1,SHA224/256384/512 Dedicated Security Controller for Flashless SHE and HSM support, Trustzone, RTIC Built-in ECDSA/DSa protocol support See the security reference manual for this chip for a full list of security features System Control 2x1C tightly coupled with Cortex-M4 cores(1x per Cortex M4F core) Sk the tightly coupled M4 2C ports cannot be used for general-purpose use ontrol unit(SC∪U) Power control clocks reset Boot roms PMIC interface Resource domain controller i MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 0, 10/2019 NⅩ P Semiconductors Introduction Table 1.i. MX 8Quad Plus advanced features (continued) Function Feature 1x PCle 3.0(2-lanes) Can be used as two Pcle 3.0 controllers with one-lane, independent operation 1×USB3.0 with Phy 2X USB 2.0(1 with PHY, 1 with HSIC) PCle 3.0 one-ane. This is in addition to the standard pcl 0 controller 2x 1 Gb Ethernet with AVB(can be used as 10/100 Mbps ENET with AVB) 3X CAN/CAN-FD 1x Media Local Bus(MLB150) 8X UARTS 5× UARTS(2× with hardware flow contro 2X UARTs tightly coupled with Cortex-M4 F cores(1x per Cortex-M4F core) 1x UART tightly coupled with SCU 18×P2c 5x General-Purpose I-C(full-speed with DMA support Low-speed l-C without DMA suppor 2× master2 C in MIPl-DS(1× per instance) 4× master2 C in LVDS(2× per instance) 2x master 2C in HDMi-TX 2× master2 C in miP-CS(1× per instance) Note: Although low-speed Cs can be made available for general purpose use which requires the associated PHY (for example, MIPI)to be powered on, it is not recommended Note: I/0 muxing constraints prevent using all ICs simultaneously 2x 12C tightly coupled with Cortex-M4 cores(1x per Cortex M4F core Note: The tightly coupled M4 12C ports cannot be used for general purpose use 1x12C tightly coupled with SCU for communication with the PMIC Not general purpose and not available for non-PMIC uses 4X SAl (SAlO and SAl1 are transmit/receive SAl2 and SAl3 are receive only) 2x Enhanced Serial Audio Interface(ESAl) X ASRC (Asynchronous Sample Rate Converter)(note: no l/O signals are directly connected to this module) 1×SPDF( Tx and rx 2x 4-channel Adc converters 3.3 V/1.8V GPIO 4x PWM channels 1×6×8KPP( Key Pad Port) 1x MQS(Medium Quality Sound) 4×SP Packaging Case FCPBGA29 X 29 mm, 0.75 mm pitch i MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 0, 10/2019 NXP Semiconductors Introduction 1.1 Ordering Information FororderinginformationcontactanNxprepresentativeatnxp.com Table 2. i MX 8QuadPlus Orderable part numbers Cortex-A72 Cortex-A53 Cortex-M4F Options Speed emperature Part number Speed Speed Grade Grade Grade Package Grade MIMX8QP5AVUFFAB With VPU,I 1.6 GHz 1.26 GHz 266 MHz Automotive 29 mm X 29 mm, 0.75 mm GPU pitch, FCPBGA (lidded MIMX8QP6AVUFFAB With VPU,I 1.6 GHz 1.26 GHz 266 MHz Automotive 29 mm X 29 mm, 0.75 mm GPU. DSP pitch, FCPBGA (lidded 1.2 System Controller Firmware(ScFW) Requirements The i MX& and 8X families require a minimum Scf W release version for correct operation and to prevent potential reliability issues The SCFW is released as part of a board Support Package(.g. Linux, Android) which may vary in version number for a specific BSP For example, NXP Yocto Linux release 4.14.98 2.0.0 GA contains SCFW version 1.2.7, whereas NXP Yocto linux release 4 14.78 1.0.0GA contains scfw version 1.1.6 The released ScFW version associated within each bsp is the minimum version required to correctly support the wider bsp functionality Customers should always check that they are using the specific scf w binary delivered within their chosen BSP release. Customers should not mix newer bsp versions with older revisions of the scfw 1.3 Related resources Table 3. related resources Ty Descripti Reference manual The i MX 8DualX8Dua/XPlus/8 QuadXPlus Applications Processor Reference Manual (IMX8DQXPRM) contains a comprehensive description of the structure and function (operation) of the Soc Data sheet This data sheet includes electrical characteristics and signal connections Chip errata The chip mask set errata provides additional and/or corrective information for a particular device mask set Package drawing Package dimensions are provided in Section 6, "Package information and contact assignments". Hardware guide Contact an NXP representative for access i MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 0, 10/2019 NⅩ P Semiconductors Architectural overview 2 Architectural overview The following subsections provide an architectural overview of the i MX 8QuadPlus processor system i MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 0, 10/2019 NXP Semiconductors Architectural overview 2. 1 Block Diagram The following figure shows the functional modules in the processor system CPU1 Platform 2x User CM4 Complexes CPU2 Platform M4 Flatform 4x ARM Cortex-A53 2x ARM Cortex-A72 4 CPU NEON VEP NEON VEP MNCAU (each) 6KB code$ 16KB systemS 32KB IS 32KB DS 48KB|$ 32KB DS 256KB TCM W/ECC 1MB L2 WiECC 1MB L2 W/optional ECC WDOG 1 GPIO LPUAR LPrC Cache Coherent Interconnect(CC1-400) 12C W/ DMA DMA Subsystem External Memory Interface ARt (5 Mb/s) 2X ADC zx eDMA 5X LPUART 5x LP 2C CAN/ CAN-FD ZX FTM 64-bit LPDDR4 ADC 2x EVM SIM 3x FlexCAN[ 4X LPSPI d connole 1600MHz channels ear Audio Subsystem 3.0 SPDIF TX/ RX 2X ASR SPDIF HDMI TX S 2 lane ESAI TX, RX 2X ESAl MOS [2x eDMA 2x PCle 1 lane each 2x SAI TX/ RX 8X SAI 6x GPT Audio Mixe SSI BUS 1x PCle 3.0 (1 lane) RAW ONFI 3.2 Connectivity Subsystem VPU Subsystem 2X LVDS 圖 1/2 LVDS TX NAND Flash Video Processing TX 5.1sD30 VPU LPI2d 2x SD 3.D(UHS-1) 1x USB 30 PHY 「3× USDHC Display Controllers 12C HIF14 DS Host hsic 2x DPU (4x LCD) 2x MIPI 2x MIP CSI2 32KB IS 48KB DS (4-lanes) 1x USB 2.0 2X USB2 512KB SRAM 64KE TCM ng Unit MLB/MOST 2x ENET MIPI Display 150+ DICP 2x GPU M-lanes) 1010011000M Ethernet AVB System Control Unit pPzk→ 1 x 12C A1×|2C SCU CM4 Complex nternal Memory HDMI TX M4 Platform HDMI OCRAM(256KB eDP Boot ROM Power Mgmt] M4 CPU DisplayPort 1.3) PMIC V/F 16KB code$ 16KB sys:emS SECO 256KB TCM W/ECC (LSIO)Subsystem 6x& Keypad 24M and 32 XTALOSC 4x PWM ADMController 32-bit GPIO 14X MU 5X GPT FUART IPIC RGPIO2x MI CAM|(MO→) x Cuad sPl/ 1x Octal SPl NOR Flash RNG 1×UART[1x1C|[1XGP0 JTAG H265Dec(4k60) Vulkan, OGLES 3.2 W/ AEP amper H264Dec(1080p60) OCL 20 VG.1 Detection (ECC, RSA H264Enc(1080p30) 2D Blit Engine Secure RTc 64k Secure i MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 0, 10/2019 NⅩ P Semiconductors Modules list Figure 1.i. MX 8QuadPlus System Block Diagram 3 Modules list The i MX 8QuadPlus processors contain a variety of digital and analog modules. This table describes the processor modules in alphabetical order. Table 4.iMX BQuad Plus modules list Block Block name Mnemonic Brief Description ADC Analog-to-Diqital The analog-to-digital converter(ADC) is a successive approximation AdC Converter designed for operation within a SoC APBH-DMA NAND Flash and BCH The AHB-to-APBH bridge provides the chip with a peripheral attachment bus ECC DMA Controller running on the AHB's HCLK, which includes the AHB-to-APB PlO bridge for a memory-mapped l/o to the APB devices, as well as a central dma facility for devices on this bus and a vectored interrupt controller for the arm core A53 Arm(CPU1) CPU cluster embedding 4x Cortex-A53 CPUs with a 32KB L1 instruction cache and a 32kb data cache The cpus share a 1 mb l2 cache A72 Arm( CPU2) CPU cluster embedding 1x cortex-A72 CPU with a 48 KB l 1 instruction cache and 32 kB data cache. The cpu has a 1mb l2 cache ASRC Asynchronous Sample The Asynchronous Sample Rate Converter(ASRC)converts the sampling rate of Rate Converter a signal associated to an input clock into a signal associated to a different output clock. The aSRc supports concurrent sample rate conversion of up to 10 channels of about-120dB THd+N. the sample rate conversion of each channel is associated to a pair of incoming and outgoing sampling rates. The ASrC supports up to three sampling rate pairs BCH-62 Binary-BCH ECC The BCH62 module provides up to 62-bit ECC for NAND Flash controller(GPMI2 Processor CAAM Cryptographic CAAM is a cryptographic accelerator and assurance module CAAM implements Accelerator and several encryption and hashing functions, a run-time integrity checker, and a Assurance module Pseudo Random Number Generator(PRNG) CAAM also implements a Secure Memory mechanism In this device the security memory provided is 64 KB CTI Cross Trigger Interface CTI sends signals across the chip indicating that debug events have occurred. It is used by features of the coresight infrastructure CTM Cross Trigger Matrix Cross Trigger Matrix IP is used to route triggering events between CTIs DAP Debug Access port The DAP provides real-time access for the debugger without halting the core to System memory and peripheral registers All debug configuration registers The daP also provides debugger access to JTAG scan chains DC Display contro‖er Dual display controller DDR Controller DRAM Controller Memory types: LPDDR4 Two channels of 32-bit memory LPDDR4 up to 1.6 GHz i MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 0, 10/2019 NXP Semiconductors Modules list Table 4.iMX 8QuadPlus modules list (continued) Block Block Name Mnemonic Brief Description DPR Display/Prefetch/ display output. Raster source buffers can also be prefetched unconverted. he The dPR prefetches data from memory and converts the data to raster format Resolve resolve process supports graphics and video formatted tile frame buffers and converts them to raster format. Embedded display memory is used as temporary storage for data which is sourced by the display controller to drive the display eDMA Enhanced direct 4x eDMA with a total of 128 channels(note: all channels are not assigned; see Memory Access the product reference manual for more information 4x instances with 32 channels each Programmable source, destination addresses, transfer size, plus support for enhanced addressing modes Internal data buffer, used as temporary storage to support 64-byte burst transfers, one outstanding transaction per DMA controller Transfer control descriptor organized to support two-deep, nested transfer operations Channel service request via one of three methods Explicit software initiation Initiation via a channel-to-channel linking mechanism for continuous transfers Peripheral-paced hardware requests (one per channel) Support for fixed-priority and round-robin channel arbitration Channel completion reported via interrupt requests Support for scatter/gather DMA processing Support for complex data structures via transfer descriptors Support to cancel transfers via software or hardware Each eDMA instance can be uniquely assigned to a different resource domain, security(tz) state, and virtual machine In scatter-gather mode, each transfer descriptor's buffers can be assigned to different smmu translation ENET Ethernet controller 2x 1 Gbps Ethernet controllers supporting RGMI + AVB(Audio Video Bridging IEEE 802.1Qav ESAL Enhanced Serial Audio The Enhanced Serial Audio Interface(ESAl)provides a full-duplex serial port for Interface serial communication with a variety of serial devices, including industry-standard codecs, SPDIF transceivers, and other processors the esal consists of independent transmitter and receiver sections, each section with its own clock generator. All serial transfers are synchronized to a clock. Additional synchronization signals are used to delineate the word frames. The normal mode of operation is used to transfer data at a periodic rate, one word per period. the network mode is also intended for periodic transfers; however, it supports up to 32 words( time slots)per period. This mode can be used to build time division multiplexed (tDm)networks. In contrast, the on-demand mode is intended for non-periodic transfers of data and to transfer data serially at high speed when the data becomes available The Esal has 12 pins for data and clocking connection to external devices FTM FlexTimer Provides input signal capture and PWM support FlexCAN Flexible Controller Area Communication controller implementing the CAN with Flexible Data rate(CAN FD) Network protocol and the Can protocol according to the can 2.0B protocol specification i MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 0, 10/2019 NⅩ P Semiconductors 9 Modules list Table 4.iMX 8QuadPlus modules list (continued) Block Block Name Mnemonic Brief Description FlexSpi(Quad Flexible Serial Flexible sequence engine to support various flash vendor devices, including SPl/Octal SPI)Peripheral Interface Hyper Bus TM devices Support for FPGA interface Single, dual, quad, and octal mode of operation DDR/DTR mode wherein the data is generated on every edge of the serial flash clock Support for flash data strobe signal for data sampling in DDR and sdR mode Two identical serial flash devices can be connected and accessed in parallel for data read operations, forming one(virtual) flash memory with doubled readout bandwidth GIC Generic Interrupt The GiC-500 handles all interrupts from the various subsystems and is ready for Controller virtualization GPIO General Purpose l/0 Used for general purpose input/output to external devices. Each GPIO module Modules supports 32 bits of wO GPMI General Purpose Media The GPMI module supports up to 8X NAND devices. 62-bit ECC (BCH) Interface encryption/decryption for NAND Flash controller(GPMI). The GPMI supports separate DMA channels per NANd device GPT General Purpose Timer Each GPT is a 32-bit"free-running"or"set and forget"mode timer with programmable prescaler and compare and capture register. A timer counter value can be captured using an external event and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. When the timer is configured to operate in"set and forget mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention the counter has output compare logic to provide the status and interrupt at comparison. This timer I can be configured to run either on an external clock or on an internal clock GPU Graphics Processing 2x GC7000XSVX GPUs with 8 shaders each that can run either independently or in"dual-mode" with 16 shaders DMI TX/ HDMI TX interface HDMI transmitter, Display Port 1.3 and embedded Display port 1.4 DP/eDP HiFi 4 DSP Audio Processor A highly optimized audio processor geared for efficient execution of audio and voice codecs and pre-and post-processing modules to offload the arm core 12 C Interface C provides serial interface for external devices lEE Supports direct encryption and decryption of FlexsPl memory type Provides decryption services (lower performance)for DRAM traffic Supports Io direct encrypted storage and retrieval Support for a number of cryptographic standards 128/256-bit AES Encryption(AES-CTR, AES-XTS mode options Multiple keys suppo Loaded via secure key channel from security block Key selection is per access and based on source of transaction IOMUXC IOMUX Control This module enables flexible O multiplexing. Each l/0 pad has default and several alternate functions. The alternate functions are software configurable JPEG/dec MJPEG engine for Provides up to 4-stream decoding in parallel decode i MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 0, 10/2019 10 NXP Semiconductors

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