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安森美半导体ESD保护器件ESD7L5.0-D 数据手册.pdf
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详细说明:安森美半导体ESD保护器件ESD7L5.0-D 数据手册pdf,安森美半导体ESD保护器件ESD7L5.0-D 数据手册ESD7L50DT5G
IEC 61000-4-2 Spec
IEC61000-4-2 Waveform
Test
First peak
Voltage
Current Current at Current at
100%
Level
(kv)
30ns(4)60ns(A)
7.5
2
4
15
8
4
3〔
3
225
12
6
8
30
16
8
I
10%
0.7 ns to 1 ns
Figure 3. IEC61000-4-2 Spec
ESD Gun
TVS
Oscilloscope
日已已日○
50g
Cable<50 Q
吕Q冒Q8
igure 4. Diag
ESD Test Setup
The following is taken from Application Note
systems such as cell phones or laptop computers it is not
AND8308/D-Interpretation of Datasheet Parameters
clearly defined in the spec how to specify a clamping voltage
for esd devices
at the device level ON Semiconductor has developed a way
ESD Voltage Clamping
to examine the entire voltage waveform across the Esd
For sensitive circuit elements it is important to limit the
protection diode over the time domain of an esd pulse in the
voltage that an IC will be exposed to during an ESd event
form of an oscilloscope screenshot, which can be found on
to as low a voltage as possible. The ESd clamping voltage
the datasheets for all esd protection diodes. For more
is the voltage drop across the esd protection diode during
information on how on Semiconductor creates these
an Esd event per the IEC61000-4-2 waveform. Since the
screenshots and how to intcrprct them plcasc refer to
IEC61000-4-2 was written as a pass/fail spec for larger
AND8307/D.
PEAK VALUE IRSM 8 us
80
PULSE WIDTH(tp)IS DEFINED
ucu02.xua8
AS THAT POINT WHERE THE
70
PEAK CURRENT DECAY =8 us
60
HALF VALUE IRSM/2 20 us
50
30
20
10
0
60
t, TIME (us)
Figure 5. X 20 Hs Pulse Waveform
http://onsemi.com
3
ESD7L50DT5G
PACKAGE DIMENSIONS
SOT-723
CASE 631AA-01
SSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM
b1
A
THICKNESS OF BASE MATERIAL
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH PROTRUSIONS OR GATE BURRS
E
MILLIMETERS
INCHES
DIM MIN NOM MAX MIN NOMMAX
045050055001800200022
b10250.31037001000120015
中|0.08(002×Y
c0070120.17000280.001700067
0.750.800850030032
0. 40 BSC
0.016 BSC
E1.151.20|1.25004500470.049
0.150.200.25000590.00790008
SOLDERING FOOTPRINT*
0.40
0.0157
040
0.0157
0.039
040
015
0.0157
0.0157
SCALE 20: 1
nches
*For additional information on our Pb-Free strategy and soldering
details, please download the oN Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and (N arc registered trademarks of Semiconductor Components Industrics, LLC (SCILLC). SCILLC reserves the right to make changos without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product ar circuit, and specifically disclaims any and all liability, including without imitation special, consequential or incidental damages
Typical " parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
d for each custo
scillA d
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in vhich the failure of the SCILLc product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLc and its oticers, employees, subsidiaries attiliates
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ESD7L5.0D/D
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