ILI9225G_DS_V0.09_.pdfILI9225G 显示屏驱动ic资料，包含各个寄存器设置

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详细说明：ILI9225G 显示屏驱动ic资料，包含各个寄存器设置参数说明，参照驱动寄存器，设置自己显示效果。ILTEK a-Si TFT LCD Single Chip Driver I Love innovation 176RG Bx220 Resolution and 262K color |9225G 8.2.10. Oscillator Control(ROFh) 68 8211. Power Contro1(R10h)…………… 69 8212. Power Control2(R11h)…… 69 8.2.13. Power Control 3(R12h). 69 8.2.14. Power Control 4(R13 70 82.15. Power control5(R14h)……,…,…,…,…,…,…,…,… ..70 8216. RAM Address Set(R2Oh,R21h)…...… 72 8. 2.17. Write Data to GRAM(R22h) ·:::::::·:..: .72 8. 2.18. Read Data from GRAM(R22h) 72 8.2.19. Gate Scan Control(R30h 3 8.2.20. Vertical Scroll Control 1(R31h, R32h 74 8.221. Vertical Scroll Control1(R33h)……… 74 8.2.22. Partial Screen Driving Position(R34h, R35h) 75 8.2.23. Horizontal and Vertical RAM Address Position(R36h/R37h, R38h/R39h) 76 8.2. 24. Gamma Control(R50h w R59h 77 8.225. NV Memory Data Programming(R60h)…… 78 8. 2.26. NV Memory Control(R61h 78 8. 2.27. NV Memory Status(R62h 78 8.2.28. NV memory Protection Key(R63h) 1 8.2. 29. ID Code(R65h, Read Only) 8.2.30. SPI Read/write Control (R66h, Write Only) 79 9. NV Memory Programming Flow 80 10 GRAM Address Map& Read/write 81 1. Window Address function ..85 2. Gamma Correction 86 13. Application.. 103 13.1. Configuration of Power Supply Circuit 103 13.2. Voltage Generation 105 13.3. Power Supply Configuration.…… 106 13.4. STB Mode 107 14.E| ectrical characteristⅰcs… 108 14.1. Absolute Maximum Ratings 108 14.2. DC Characteristics 109 14.3. Reset Timing characteristics 109 14.4. AC Characteristics 14.4.1. i80-System Interface Timing Characteristics 110 14.4.2. M68-System Interface Timing Characteristics.... 112 14.4.3. Serial Data Transfer Interface Timing characteristics 113 14.4.4. RGB Interface Timing characteristics 114 The information contained herein is the exclusive property of Ill Technolo p. and shall not be distributed, reproduced, or disclo sed in whole or in part without prior written permis sion of ll/Technology corp Page 2 of 117 Version: 0.09 ILTEK a-Si TFT LCD Single Chip Driver I Love innovation 176RG Bx220 Resolution and 262K color |9225G Figures FIGUREI SYSTEM INTERFACE AND RGB INTERFACE CONNECTION FIGURE2 8-BIT SYSTEM INTERFACE DATA FORMAT 23 FIGURES 16-BIT SYSTEM INTERFACE DATA FORMAT FIGUREA 180 16/18-BIT SYSTEM INTERFACE TIMING 26 FIGURES M68 16/18-BIT SYSTEM INTERFACE TIMINO 26 FIGURE6 9-BIT SYSTEM INTERTACE DATA FORMAT 27 FIGURET 8-BIT SYSTEM INTERFACE DATA FORMAT FIGURE& DATA TRANSFER SYNCHRONIZATION IN 8/9-BIT SYSTEM INTERFACE FIGURE9 DATA FORMAT OF SPI INTERFACE 31 FIGURElO DATA TRANSMISSION THROUGH SPI. 65 COLOR 32 FIGURElI DATA TRANSMISSION TIIROUGII SPL 262K COLOR 33 FIGUREI2 RGB INTERFACE DATA FORMAT FIGURE1 3 GRAM ACCESS AREA BY RGB INTERFACE .…………40 FIGURE14 TIMING CHART OF SIGNALS IN 18-/16-BIT RGB INTERFACE MODE FIGURE15 TIMING CIIART OF SIGNALS IN 6-BIT RGB INTERFACE MODE 42 FIGURE I6 EXAMPLE OF UPDATE THE STILL AND MOVING PICTURE 43 FIGUREIT INTERNAL CLOCK OPERATION/RGB INTERFACE MODE SWITCHING figurei& GRAM ACCESS BETWEEN SYSTEM INTERFACE AND RGB INTERFACE FIGURE19 RELATIONSHIP BETWEEN RGB I/F SIGNALS AND LCD DRIVING SIGNALS FOR PANEL............. 48 FIGURE20 REGISTER SETTING WITII SERIAL PERIPIIERAL INTERFACE (SPD 49 FIGURE2I REGISTER SETTING WITH ISO/M68 SYSTEM INTERFACE FIGURE22 REGISTER READ/ WRITE TIMING OF I&O SYSTEM INTERFACE 51 figure2 3 reGisteR READ/Write TIMING OF M68 SYSTEM INTERFACE 2 FIGURE24 INTERLACE SCAN OF AC DRIVE 60 FIGURE25 OUTPUT TIMING OF INTERLACE GATE SIGNALS(THREE-FIELD IS SELECTED)........ 60 FIGURE26 AC DRIVING ALTERNATING TIMING 61 FIGURE2 GRAM ACCESS DIRECTION SETTING .62 Figure28 SCANNING START POSITION FOR GATE DRIVER FIGURE29 GRAM ACCESS RANGE CONFIGURATION FIGURESO GRAM READ/WRITE TIMING OF ISO-SYSTEM INTERFACE 81 FIGURE3 1 GRAM READ/WRITE TIMING OF M68-SYSTEM INTERFACE FIGURE32180- SYSTEM INTERFACE WITH18-/9 BIT DATA BUS(SS=0”,BGR=”0”).………83 FIGuRE33180- SYSTEM INTERFACE WITH18-/9 BIT DATA BUS(SS=1”,BGR=”1”) 84 FIGURE34 GRAM ACCESS WINDOW MAP 85 FIGURES5 GRAYSCALE MAPPING FIGURE36 GRAYSCALEⅤ OLTAGE GENERATION.…… FIGURE37 GRAYSCALE VOLTAGE ADJUSTMENT I The information contained herein is the exclusive property of Ill Technolo p. and shall not be distributed, reproduced, or disclo sed in whole or in part without prior written permis sion of ll/Technology corp Page 3 of 117 Version: 0.09 ILTEK a-Si TFT LCD Single Chip Driver I Love innovation 176RG Bx220 Resolution and 262K color |9225G figure3 8 GRAYSCALE VOLTAGE ADJUSTMENT 2 FIGURE39 GAMMA CURVE ADJUSTMENT FIGURE40 RELATIONSHIP BETWEEN GRAM DATA AND OUTPUT LEVEL FIGUREAI POWER SUPPLY CIRCUIT BLOCK 04 FIGURE42 VOLTAGE CONFIGURATION DIAGRAM l05 FIGURE43 POWER ON/OFF SEQUENCE 106 FIGURE44 STB MODE REGISTER SETTING SEQUENCE 107 FIGURD45 180-SYSTEM BUS TIMING .110 FIGURE46 M68-SYSTEM BUS TIMING FIGURE4 M68-SYSTEM INTERFACE TIMING 112 FIGURE48 SPI SYSTEM BUS TIMING.1111……13 FIGURE49 RGB INTERFACE TIMING…… ∴14 The information contained herein is the exclusive property of Ill Technolo p. and shall not be distributed, reproduced, or disclo sed in whole or in part without prior written permis sion of ll/Technology corp Page 4 of 117 Version: 0.09 ILTEK a-Si TFT LCD Single Chip Driver I Love innovation 176RG Bx220 Resolution and 262K color |9225G Introduction ILI9225G is a 262, 144-color one-chip Soc driver for a-TFT liquid crystal display with resolution of 176RGBx220 dots, comprising a 528-channel source driver, a 220-channel gate driver, 87120 bytes RAM for graphic data of 176RGBx220 dots, and power supply circuit ILI9225G has four kinds of system interfaces which are i80/M68-system MPU interface(8-9-/16-718-bit bus width), serial data transfer interface(SPl)and RGB 6-116-718-bit interface(DOTCLK, VSYNC, HSYNC ENABLE, DB[17: 01) In RGB interface, the combined use of high-speed RAM write function and widow address function enables to display a moving picture at a position specified by a user and still pictures in other areas on the screen simultaneously, which makes it possible to transfer display the refresh data only to minimize data transfers and power consumption ILI9225G can operate with low 1O interface power supply up to 1.65V, with an incorporated voltage follower circuit to generate voltage levels for driving an LCD. The IL19225G also supports a function to display in 8 colors and a standby mode, allowing for precise power control by software. These features make the ILI9225G an ideal LCd driver for medium or small size portable products such as digital cellular phones or small PDA, where long battery life is a major concern 2 Features o Single chip solution for a liquid crystal QCIF+ TFT LCd display 9 176RGBX220-dot resolution capable of graphics display in 262, 144 color Incorporate 528-channel source driver and 220-channel gate driver o Internal 87, 120 bytes graphic RAM High-speed RAM burst write function ◆ System interfaces 180 system interface with 8-/9-/16-/18-bit bus width M68 system interface with 8-19-/16-/18-bit bus width Serial Peripheral Interface(SPl) RGB interface with 8-/16-718-bit bus width(VSYNC, HSYNC, DOTCLK, ENABLE, DB[17: 0] o Reversible source/gate driver shift direction o Window address function to specify a rectangular area for internal GRAM access Abundant functions for color display contro y-correction function enabling display in 262, 144 colors Line-unit vertical scrolling function o Partial drive function, enabling partially driving an LCD panel at positions specified by user Incorporate step-up circuits for stepping up a liquid crystal drive voltage level up to 6 times (X6) Power saving functions >8-color mode standby mode The information contained herein is the exclusive property of Ill Technolo p. and shall not be distributed, reproduced, or disclo sed in whole or in part without prior written permis sion of ll/Technology corp Page 5 of 117 Version: 0.09 ILTEK a-Si TFT LCD Single Chip Driver I Love innovation 176RG Bx220 Resolution and 262K color |9225G o LOw-power consumption architecture Low operating power supplies lOVcc(VDD3)=1.65 3.3V(interface IO) Vci=2.5~3.3V Low voltage drive: AVDD(AVDD)=4.5-5.5V The information contained herein is the exclusive property of Ill Technolo p. and shall not be distributed, reproduced, or disclo sed in whole or in part without prior written permis sion of ll/Technology corp Page 6 of 117 Version: 0.09 ILITEK a-Si TFT LCD Single Chip Driver I Love innovation 176RG Bx220 Resolution and 262K color |9225G 3. Block Diagram Inde Regist (R) ncs MPU W/F nWR 8-bit 6-bit 9 Control Address LCD 8-bit Registe DB[17:0 (CR) (AC) Source S[528:1 Driver SDI SPID/F RGB WF ENABLE Operation DOTCLK VSYNC F VREG1OUT TEST MODE[2: 01 Read Grayscale Latch TEST MUX[2: 0 Latch Reference TEST CSN[1: 0] Voltage GS Graphics RAM DD Regulator (GRAM) RVDD FLM LCD Gate G[220:1 RO-OSC Timing Controller Driver VCOM Charge-pump Power Circuit VCOM Generator GND The information contained herein is the exclusive property of Ill Technolo p. and shall not be distributed, reproduced, or disclo sed in whole or in part without prior written permis sion of ll/Technology corp Page 7 of 117 Version: 0.09 ILITEK a-Si TFT LCD Single Chip Driver I Love innovation 176RG Bx220 Resolution and 262K color |9225G 4. Pin Descriptions Pin Name 1o Type Descriptions Input Interface Select the MPU system interface mode IM3 IM2 IM1 IMO MPU-Interface Mode DB Pin in use 0000 M68-system 16-bit interface DB7:101,DB8:1 168-system 8-bit interf DB[17:10 0 0 i80-system 16-bit interface DB[17:10],DB8:1 0 0 1 i80-system 8-bit interface DB[17:10] 010 ID 24-bit 4 wires Serial Peripheral SDI, SDO, SCL, Interface(SPI IM2 0110 9-bit 3 wires Serial Peripheral SDA. SCL, nCs lOVcc Interface 0 18-bit 4 wires Serial Peripheral SDA. SCL nCS. RS IMO/ID Interface (D/CXI M68-system 18-bit interfac DB[17:0 1 M68-system 9-bit interface DB[17:9] 0 i80-system 18-bit interface DB17:01 1011 i80-system 9-bit interface DB[17: 9 1 I Setting invalid When the serial peripheral interface is selected, IMO pin is used for the device code ID setting A chip select signal MPU Low: the ILl9225G is selected and accessible ncS lOVe High the ILl9225G is not selected and not accessible Fix to loVcC level when not in use A register select signal MPU LoW: select an index or status register RS (D/CX) JOVcC High: select a control register Fix to gNd level when not in use In 68-system mode, this is used to select operation, read or write (RW) MPU RW nWRISGL In 80-system mode, this serves as a write strobe signal(nWR) lOVcc In SPI mode, it serves as a synchronous clock (SCL In 68-system mode, this serves as write/read enable strobe(E) MPU E nRD In 80-system mode, this serves as a read strobe signal. (nRD VCc Must be fixed to gnd level when sPl mode A reset pIl n MPU nRESET Initializes the IL9225G with a low input. Be sure to execute a IVCc power-on reset after supplying power 18-bit parallel bi-directional data bus for MPU system interface mode MPU DB[17:0] O lOVcc Serves as an input data bus for mPu wF. 8-bit I/F: DB[17: 10] is used The information contained herein is the exclusive property of Ill Technolo p. and shall not be distributed, reproduced, disclo sed in whole or in part without prior written permis sion of ll/Technology corp Page 8 of 117 Version: 0.09 ILTEK a-Si TFT LCD Single Chip Driver I Love innovation 176RGBx220 Resolution and 262K color I9225G Pin name / Type Descriptions 9-bit WF: DB[17: 9] is used 16-bit l/F: DB[17: 10] and DB[8: 1]is used 18-bit V/F: DB[17: 0] is used Serves as an input data bus for rgb i/F 6-bit interface: DB[17: 12 16-bit interface: DB[17: 13], DB[11: 1 5 18-bit intertace: DB[17: 0 Unused pins must be fixed GNd level In the 24-bit 4 wires serial peripheral interface, this pin is used as input n MPU SDISDA In the 8/9-bit serial peripheral interface, this pin is used as lOVcc i-directional data pin Fix to GNd level when not in use Serial data output (SDO)pin in serial interface operation. The data is MPU outputted on the falling edge of the SCL signal SDO lOVcc When the SP/ interface is not used, please let SDO as floating. a dot clock signal MPU DPL=0": Input data on the rising edge of dOTCLK DOTCLK IVCc DPL="1": Input data on the falling edge of DOTCLK Fix to gnd level when not in use A frame synchronizing signal MPU VSPL=“0”: Active low. VSYNC IVCc VsPL=“1”: Active high Fix to gnd level when not in use a line synchronizing signal MPU HsPL=“0": Active low. HSYNC HsPL=“1: Active high Fix to GNd level when not in use a data Enable signal in RGB interface mode LoW: Select(access enabled) ENABLE High: Not select(access inhibited) lOVcc The EPL bit inverts the polarity of the ENABLe signal Fix to GND level when not in use LCD Driving signals S528~S1 O LCD Source output voltage signals applied to liquid crystal The information contained herein is the exclusive property of Ill Technolo p. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permis sion of Il/ Technology corp Page 9 of 117 Version: 0.09

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