MT7621_ProgrammingGuide_Preliminary_Platform_decry

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详细说明：mtk 7621开发编程指导，MT7621_ProgrammingGuide_Preliminary_Platform_decrypted.pdfRalink MT7621 PROGRAMMING GUIDE A MEDIATEK COMPANY Table of contents MT7621 OVERVIEW FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS 1. MIPS 1004KC PROCESSOR 1.1 FEATURES 223557 1.2 MEMORY MAP SUMMARY 1, 3 INTERUPT TABLE SUMMARY 2. REGISTERS 2. 1 NOMENCLATURE 11 2.2 SYSTEM CONTROL 2.2.1 FEATURES 2.2.2 BLOCK DIAGRAM 12 2.2, 3 REGISTERS 2, 3 TIMER 41 2, 3. 1 FEATURES 41 2.3.2 BLOCK DIAGRAM 23. 3 REgISTERS 43 2. 4 SYSTEM TICK COUNTER 48 2. 4. 1 REGISTERS 48 25 UART LITE 50 25 1 FEATURES 50 2.5.2 REGISTERS 51 2.6 PROGRAMMABLE I/O 2.6.1 FEATURES 2.6.2 BLOCK DIAGRAM 2. 6. 3 GPIO PIN MAPPING 65 2,.6. 4 REGISTERS 67 2. C CONTROLLER 79 27. 1 FEATURES 2.7.2 LIST OF REGISTERS 2. 8 NAND FLASH INTERFACE 87 2.8. 1 FEATURES 8 2.8.2 REGISTERS 2,8. 3 PROGRAMMING GUIDE 106 2.9 NEI ECC CONTROLLER 115 29. 1 FEATURES 115 9.2 REGISTERS 116 2, 9. 3 PROGRAMMING GUIDE 130 2.10 PCM CONTROLLER 134 2.10.1 FEATURES 134 2.10.2 BLOCK DIAGRAM 134 2.10, 3 LIST OF REGISTERS 136 2.10, 4 PCM CONFIGURATION 2.11 GENERIC DMA CONTROLLER 154 PGMT7621V10_130607 Page 3 of 349 Ralink MT7621 PROGRAMMING GUIDE A MEDIATEK COMPANY 2. 11. 1 FEATURES 154 2.11.2 BLOCK DIAGRAM 154 2.11, 3 PERIPHERAL CHANNEL CONNECTION 155 2.11, 4 REGISTERS 156 2.12 SPI CONTROLLER 2.12.1 FEATURES 2.12. 2 BLOCK DIAGRAM 2.12, 3 REGISTERS 203 2. 13 12S CONTROLLER 213 2. 13. 1 FEATURES 213 2.13.2 BLOCK DIAGRAM 213 2.13, 3 REGISTERS 215 2.14 SPDIF TX 220 2. 14.1 REGISTERS 221 2.15 MEMORY CONTROLLER 235 2.15.1 FEATURES 235 2.15.2 REGISTERS 236 2. 16 RBUS MATRIX AND QOS ARBITER 2.16.1 FEATURES 319 2. 16.2 BLOCK DIAGRAM 2.16.3 REGISTERS OF QOS CONTROL 320 2. 16. 4 REGISTERS OF RBUS MATRIX 325 2.17 EXTERNAL MC ARBITER 2.17.1 REGISTERS 330 2.18 ANALOG MACRO CONTROL 2.18.1 REGISTERS 334 3. LIST 346 4. REVISION HISTORY PGMT7621V10_130607 Page 4 of 349 Ralink MT7621 PROGRAMMING GUIDE A MEDIATEK COMPANY 1 MIPS 1004Kc Processor 1.1 Features ■8-9- stage pipeline 32-bit Address Paths I 64-bit Data paths to caches MIPS32 Enhanced Architecture(Release 2)Features Standardized instruction Set Architecture Vectored interrupts and support for an external interrupt controlle Programmable exception vector base Atomic interrupt enable/disable Bit field manipulation instructions a MIPS16e Application Specific Extension 16 bit encodings of 32-bit instructions to improve code density Special PC-relative instructions for efficient loading of addresses and constants Data type conversion instructions(ZEB, SEB, ZEH, SEH) Compact jumps (JRC, JALRC) Stack frame set-up and tear down"macro instructions(SAvE and REStore) a MIPS MT Application specific Extension(ASe) Support for 2 Virtual Processing Elements (vPes) per core One Thread Context (tC) per VPE Programmable Ll Cache Sizes Individually configurable instruction and data caches 32KB ID cache 4-way set associative Up to 9 non-blocking loads Data cache supports coherent and non-coherent Write-back with write-allocation 32-byte cache line size, doubleword sectored -suitable for standard single-port SRAM Cache line locking support Non-blocking prefetches Duplicate tag array in D-cache allows coherence requests to access the cache in parallel with normal oad/ store traffie a Standard Memory Management Unit 32 dual-entry MIPS32-style jtLB per VPe with variable page sizes JTLBs are sharable under software control 4-5 entry instruction tlB data tLB a OCP Bus Interface Unit(BIU) 32b address and 64b data Supports bursts of 4x64b 8 entry write buffer- handles eviction data, intervention response, uncached, and uncached lerated store data Simple byte enable mode allows easier bridging to other bus standards Extensions for management of front side L2 cache Intervention port supports memory coherency for use in a 1004K Coherent Processing System Multiply-Divide Unit Maximum issue rate of one 32x32 multiply per clock Early-in divide control. Minimum 1 1, maximum 34 clock latency on divide ■ Power Control No minimum frequency Support for software-controlled clock divider Support for extensive use of fine-grain clock gating PGMT7621V10_130607 Page 5 of 349 Ralink MT7621 PROGRAMMING GUIDE A MEDIATEK COMPANY ■ EJTAG Debug Support Start, stop, and single stepping control Software breakpoints via the Sdbbp instruction Optional hardware breakpoints on virtual addresses; 0, 2, or 4 instruction and 0. 1, or 2 data breakpoints per VPE I SOC-it L2 Cache Controller 7-stage pipeline. Optional 8th stage for pipelined memory arrays. 32-bit address paths, 256-bit internal data paths 8-way set associativity Cache size: 256KB Line Size: 32 bytes(4 doubleword) ETAG ETAG cac Trace CoeXtend 8-64KB Off-Chip Debug I MT control I TAP 4 way set associative block Scratchpad RAM IC Dispatch Unit Fetch Unit B entry merging write buffer, 6-10 Execution Unit (RF per TC, ALU MMU (per VPE) Shift, etc) 16-64 entry JTLB FPU CP2 Non blocking Load/Store Unit 4-8 outstanding misse atchpad RAM System Cop D-cache 864KB 4 way set associative Inter- Thread Communication Unit 1004K CPU Block Diagram PGMT7621V10_130607 Page 6 of 349 Ralink MT7621 PROGRAMMING GUIDE A MEDIATEK COMPANY 1.2 Memory Map Summary Start End Size Description 0 1BFFFFFF 448M DRAM Direct Map 1 C000000 1DFFFFFF 32M <> 1E0000001E0000FF 256 SYSCTL 1E0001001E0001FF 256 TIMER 1E000200 1E0002FF 25 INTCTL 1E000300 1E0003FF 256 Flash Controller(NOR/SRAM/SDRAM) 1E0004001E0004FF 256 Rbus Matrix ctrl 1E000500 1E0005FF 256 MIPS CNT 1E000600 1E0006FF GPIO 1E000700 1E0007FF S/PDIF 1E0008001E0008FF 256 DMA CFG ARB 1E000900 1E0009FF 256 120 1E000A001E000AFF 256 S 1E000B001E000BFF 256 SPI CSR 1E000c001E000CFF 256 UARTLITE 1 1E000D001E000DFF256 UARTLITE 2 1E000E00 1EOO0EFF UaRtlITE 3 1E000F001E000FFF 256 ANACTL 1E001000 1E0017FF <> 1E0018001E001FFF KKk水 <> 1E0020001E0027FF2K PCM(up to 16 channel 1E002800 1E002FFF Generic dma up to 64 channel 1E003000 1E0037FF 2K NAND Controller ( actually 1k in Module 1E003800 1E003FFF 2K NAND ECC Controller *(actually 3K in module) 1E004000 1E004FFF Crypto engine 1E0050001E005FFF 4K MEM CTRL (DDRII/DDRII) 1E006000 1E006FFF 4K EXT MC ARB 1E0070001E007FFF4K HS DM 1E0080001E00FFFF32K <> 1E010000 1EOFFFFF 960K <> 1E100000 1E10DFFF 56K Frame Engine(FE SRAM: OX1E1080000X1E10DFFF) 1E10E000 1E10FFFF 8K PCle sram 1E1100001E117FFF 32K Ethernet gmac 1E1180001E11FFFF 32K ROM 1E1200001E12FFF 64K <> 1E1300001E137FFF32K SDXC 1E1380001E13FFFF 32K <> 1E140000 1E17FFFF 256K PCI Express 1E180000 1E1BFFFF 256K <> 1E1C0000 1E1FFFFF 256K USB Host(U2+U3) 1E200000 1E23FFFF 256K <> 1E240000 1E24FFFF 64K <> PGMT7621V10_130607 Page 7 of 349 Ralink MT7621 PROGRAMMING GUIDE A MEDIATEK COMPANY 1E250000 1E7FFFFF 5824K <> 1E800000 1EBFFFFF 4M PCIE Direct access for inic 1EC00000 1FBBFFFF 16128K <> 1FBC0000 1FBDFFFF 128 CM GIC 1FBE0000 1FBEFFFF 64K <> 1FBF0000 1FBF7FFF 32K CM CPC 1FBF8000 1FBFFFFF 32K CM GCR 1FC00000 1FFFFFFF 4M ROM/SPI FLASH Direct Access 2000000023 FFFFFF 64M DRAM Re-Map 24000000 5FFFFFFF 960M <> 600000006 FFFFFFF 256M PCIE Direct Access 70000000 7FFFFFFF 256M <> PGMT7621V10_130607 Page 8 of 349 Ralink MT7621 PROGRAMMING GUIDE A MEDIATEK COMPANY 1.3 Interupt Table Summary MIPS1004Kc All the system interrupts are n GIC GIC connected to PEO (Shared) (Local) Pin1 (GIC INTO-63) Ping SI_ FDCInt, SI PCInt, SI TimerInt, SI SWInt[1: O MT7621 Interrupt architecture Map to Pin Moudle Source pin Level/Edge Map to VPE (Compatibility) GIC INTO MIPS1004Kc SI CM Err Level PEO Pin(0×0500) GIC INT1 MIPS1004Kc CM PCInt Le PEO Pin(0×0504) GIC INT2 Pin0(0x0508 GIC InT3 int req Leve PEO Pin3(0×050C) GIC INT4 PCIE pcie int rego Level PEO Pin4(0×0510) GIC INT5 MIPS1004Kc/AUX STCK ST TimerInt/MIPS CNTInt Level VPEO Pin5(0×0514 GIC INT6 Pin0(0x0518) GIC INT7 Pin00×051C GIC InT8 Pin0(0×0520) GIC INT9 Pin0(0×0524 GIC INT10 PCM pcm I Level PEO Pin(0x0528) GIC INT11 HSDMA hs dma int Level VPEO Pino(0x052C GIC INT1 GPIO gpio int Level PEO Pn0(0x0530 GIC INT13 GDMA gdma int Leve PEO Pn00×0534) GIC INT14 NE nd integ PEO Pin0(0x0538 GIC INT15 NFIECC niece Integ Leve PEO Pino(0x053C GIC INT16 VPEOPint(×0540) GIC INT17 SPI spi int Level PEO Pn0(0×0544 gic inTial S/PDIF sodif int Level PEO pin0(0x0548 GIC INT191 CRYPTO crypto int evel VPE0 Pind×54C) GIC INT20 SDXC sdxc int Level VPE0Pin0×0550 CINT21 PCT TRL Level VPE0 PinO(0x0554) GIC INT22 USB20/3.0 usb int Level VPEo Pin00×0558》1 GIC INT23 SWITCH esw int in PEC Pin0(0×055C GIC INT24 PCIE1 pcie int req1 evel VPE0Pn40×0560 GICINT25 PCIE2 ocie int reg2 Level VPEO Pin4(0×0564) GIC INT26 UART-LITE rtl1 int Level PEO Pin0(0×0568) GIC INT27 UART-LITE uart int VPEO Pin(0×056C GIC INT28 UART-LITE uartI3 int Level VPEO Pin0(0x0570 GICINT29 TIMER latimer int Level VPEO Pin0(0×0574) GIC INT30 TIMER timer0 int Level PEO Pin0(0×0578) GIC INT31 TIMER timer1 int Level PEo Pin0(0×057c PGMT7621V10_130607 Page 9 of 349 Ralink MT7621 PROGRAMMING GUIDE A MEDIATEK COMPANY Map to Pin Moudle Source Pin Level/Edge Map to VPE (Compatibility GIC INT32 Pin0(0x0580) GIC INT33 Pin0(0x0584) GIC INT34 Pin0(0×0588) GIC INT35 Pin00×058C GIC INT36 Pin(0x0590) GIC INT37 Pin0(0x0594 GIC INT38 Pin00x0598) GIC INT39 PinO(0×059C GIC INT40 pn(o×O5A0 GIC INT4. Pin00×05A4) GIC INT42 Pin(0×05A8) GIC INT43 PinO(OX05AC) GIC INT44 Pin0(0×05B0) GIC INT45 Pin0(0×O5B4 GIC INT46 Pin(0×O5B8) GIC INT47 Pin0(0×05BC GIC INT48 Pin0(0×05c0) GIC INT49 PinO(0x05C4 GIC INT50 PinO(0x05C8 GIC INT51 Pin00×05CC GIC INT52 PinO(OX05D0 GIC INT53 PinO(0X05D4) GIC INT54 Pin00×05D8) GIC INT55 Pin0(0×05DC GIC INT56 MIPS1004Kc IPI0 PEO Edge VPE0Pn1(0×05E0) GIC INT57 MIPS1004Kc IPIO VPE1 Edge VPE1 Pin1(0×05E4) GIC INT58 MIPS1004Kc IPIO VPE2 Edge VPE2 Pin1(0×05E8) GIC INT59 MIPS1004Kc IPIO VPE3 Edge VPE3 Pin 1(0xo5EC) GIC INT60 MIPS1004Kc IPI1 VPEO Edge PEO Pin 2(0x05FO) GIC INT61 MIPS1004Kc IPl1 VPE1 Edge VPE1 Pin2(0×05F4) GIC INT62 MIPS1004Kc IPl1 VPE2 ge Pin2(0×05F8 GIC INT63 MIPS1004Kc IPl1 VPE3 Pin 2 (0x05F8) PS: the empty part means reserved PGMT7621V10_130607 Page 10 of 349

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