西门子IP242模块资料.pdf西门子IP242模块资料pdf,西门子IP242模块资料Chapte

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详细说明：西门子IP242模块资料pdf,西门子IP242模块资料Chapter Hardware Description 1.3 The AM 9513 Counter Chip 1.3.4 Hold Register (AM 9513) The AM 9513 counter chlp contains five high-speed counters There is one Hold register(H) for each of the five counters which can be programmed to perform various counting and The Hold register is used as a storage buffer for the counter scaling functions. a general description for each of the 16-bit i't:t value. The contents of the counter will be transferred to the registers that control these counters is given below Hold register via a software command. this feature allows the user to check the current value of the counter without 1.3.1 Master Mode Register (AM 9513) interrupting the counting operation The Master Mode register (MM) is used to enable and perform The Hold register cannot be read directly; its data is first special functions which are common to each individual transferred to the result of counter register. You must then counter. There is one master mode register for all five counters read the result of counter register to retrieve the value stored These functions include in the hold register. The result of counter register is described in Section 1.5.1 Defining and enabling the inputs, outputs, and scaling factor for Scaler 2, Thls is the main function of the mm register 1.3.5 Alarm Register (AM 9513) i Providing an enable bit for the output of Scaler 2. the output of Scaler 2 will be referred to as foUt There are two Alarm registers(A); one for Counter 1, and one for Counter 2. The Alarm register is used in conjunction with Providing enable bits for the two comparators that are the comparators available to Counters 1 and 2. the Alarm available for Counters 1 and 2 register is used to store the value which will be compared I Providing a bit to select the operating mode of Scaler 2. wlth the counter value. If the comparator Is enabled in the Either binary scaling or BCD scaling is allowed Master Mode register, the output of the counter will become active only when the alarm register value equals the counter Providing two bits which are used to control and enable the real-time clock function value. The Alarm register may also be referred to as the 1.3.2 Counter Mode Register(AM 9513) There is one Counter Mode register(CM) for each of the five 1.4 6ES5-242 Module Registers counters. The counter mode registers are used to provide The 6ES5-242 module has several registers which are not control, setup, and operation of each individual counter These functions include found in the AM 9513 or the AM 9519 chips. These registers are used for various functions which are not available on the Providing four bits to select one of 16 available pulse AM 9513 or the AM 9519, but are necessary for the operation sources to the cou module. A brief description of these registers is presente o of the AM 9519, but are necessary for the operation of the Providing a bit to enable or disable the gate control functions three bits to select the operating mode of the ol function 1.4.1 Control Register Providing a bit to select the counting pulse edge either The Control register(CTRL) is used to control various functions rising or falling edge and counter selections of the AM 9513. This register is not normally addressed directly by the user; the function blocks Providing a bit to select one of two registers from which used to communicate with the 6es5-242 module will handle the counter value can be loaded any data transfers to this register. These functions include: i Providing a bit to select one of two counting modes, either Providing three bits to select from one of eight possible continuous or. onecycle mode chip operations which include: parameter assignment, Providing a bit to select the counter s operating mode, either counter manipulation, and selection of additional functions binary or BCD counting Providing five bits, one for each counter, which are used Providing a bit to select the counting direction, either up to specify which counter or counters are to be invoived in counting or down counting the operation selected by the other three bits of the register. Providing three bits to select the output configuration of the counter 1.4.2 Function Number Register The Function Number Register (FNRis used to identify the 1.3, 3 Load Register(AM 9513) user-stored functions. these functions can be stored on a 4K byte EPROM. There is one Load register(L) for each of the five counters. The Load register is used to provide the counter with a preset count value which is set by the user Chapter 1 Hardware Description 1.4.3 Interrupt Mask Register 1.4.5 Error Signal Register The 6ES5-242 module has one 16-bit Interrupt mask register The error Signal register (FEM)is a 16-bit register which may INTM): the eight low order bits of the interrupt mask register be read to determine if one of several errors has occurred are used to enable and disable the eight interrupts generated a group interrupt will be sent to the Pc if the error bit in by the AM 9519. Only two of the eight high order bits of the the Interrupt mask register is set interrupt mask register are used. These two bits are used for enabling a group interrupt for a Ready signal and an Error signal, which will be described in detail later in this manual 1.4.6 Result of Counter Register There is one Result of Counter register(E1-E5 for each of 1.4.4 Interrupt Information Register the five counters. The Result of Counter register is used to tore the current count of the counter when the register is The Interupt Information register (INTI) is a 16-bit register read. Reading the register does not affect the operation of which is a mirror Image of the Interrupt Mask register. it is he counter used to store any interrupts that have occurred. you may read the contents of the interrupt Information register to determine The Hold register cannot be read directly its data is first which interrupt has occurred transferred to the result of Counter register You then read the Result of Counter register to retrieve the value stored in the hold register. Chapter 2 Module Setup Procedures This section will describe in detail the setup of the six switches SWITCH S1 Jumper Assignments located on the 6ES5-242 module Jumper Address 8-9 A4 2.1 Switch S1- Addressing 7-10 The s1 switch is used to select the module s address within 6-11 a PC. it is connected to the address lines a4-a11. The 5-12 addressing range is selected from 128 to 240 decimal. The 4~13 following figures show the details of the S5-150, S5-135U 3-14 and S5-115U 2-15 A10 1-16 A11 Al1 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 AO 2.2 Switch S2 Group Interrupts module address sub address NOTE If your Pc is not the S5-150S, all jumpers on Switch S2 X= irrelevant if jumper E-F is removed. if jumper E-F is should be open and the setting of switch S2 is not necessary installed, Al1-A8 should be open. Note that jumper Switch S2 is used in conjunction with the 150S PC. The 150S E-f should only be installed for the S5-210 system does not have a hardware interrupt line on the backplane of I a selected or jumper closed. a7 must be closed to have the Pc as do the 135U, 115U, and the 210 PCs. Instead the 150 an address of at least 128 uses Ibo (input byte o) to provide interrupt capabilities. To allow the use of ibo the 242 module provides special circuitry s= selectable jumpers With jumpers A6- A4 there are eight which allows it to simulate lBo different addresses selectable for the module The 150S system may contain up to eight 242 modules. If the o s represents the sub address, A3- AO. Each module has interrupt capabilities are to be used, each of the modules 16 internal addresses which are relative to the modules used within the pc must be assigned a group interrupt code address This is accomplished with switch S2 The first module used within the Pc must be assigned as the Al1 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 AO Decimal Hex Master module. If only one module is used, it must be assigned 0000000128-143XX80-X8F as the master When an interrupt occurs it will appear on IBO xXXx10010000144-159X90-X9F bit o for the module that is coded as the Master XxXX 0100000160-175XXA0-XXAF The remaining modules used in the pc will be assigned a slav xxxx 10 110000 176-191 XXB0-XXBF number, slaves 1-7. These slave numbers correspond to the XxxX 1000000192-207xxC0-XXCF remaining bits in IBO; i.e., slave 2 will be IB0.2. XXXX11010000208-223X×D0XXDF xxxx 11100000224-239 xxE0-XXEF The 150s interrupt system has a priority organization, IB0.0 XXXX11110000240-255XF0-xXF has the highest priority and 1Bo. 7 has the lowest priority. X irrelevant it jumper E-F is open. If jumper E-F is closed, the PC. the Master will have interrupt priority over the slaves jumpers must be open slave 1 will have priority over slave 2 and so on. 1= Jumper closed Also used in conjunction with switch S2 will be jumper G-H. 0= jumper open The jumper G-H is used to determine if the module is the Master or a slave. the following table reflect s the correct For the $5-210 system bus the addressing range is between settings for each of thr eight possible modules FOlxH and FFFXH. A maximum of 255 modules may be addressed 1BOx S2 Jumper Description OBx Jumper G-H 8-9 Master A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 AO 7-10 Slave 1 OB3 closed s60000 Slave 2 OB4 closed module address sub address 5-12 Slave 3 OB5 Slave 4 OB6 3-14 Slave 5 OB7 Jumper E-F should be installed for the S5-210 system 2-15 Slave 6 closed s= selectable jumpers With jumpers all -A4 there are 255 1-16 Slave 7 OB9 different addresses selectable for the module o=represents the sub address, A3-Ao. Each module has 16 internal addresses which are relative to the modules address 45 Chapter 2 Module setup Procedures Coding Rules For The Master Module s5-210 1. Jumper G-H must be open The $5-210 system has four system interrupts available and a 210 bus interrupt (PL4)available. The program response to 2. Jumper 8-9 on S2 must be ciosed. This will identify the each of the available interrupts must be written in assembly module as the Master language. The interrupt handling system for the S5-210 system 3. The remaining jumpers on S2 will be closed, unless there is beyond the scope of this manual and the reader should is a slave module assigned to that jumper; then it should refer to the instruction manual for the S5-210 system be open Jumper Description Coding Rules For Slave Modules 8-9 System Interrupt irA 1. Jumper GH must be closed 7-10 System Interrupt IRB' 6-11 2. Jumper 8-9 on S2 must be open System Interrupt IRC' 5-12 System Interrupt IRD 3. Only the jumper on $2 for the appropiate slave number -16 210 Bus Interrupt PL. 4(EANK) should be closed. The remaining jumpers on S2 must be open. s5-135U The s5-135u has only one system interrupt for each of the four NOTE available CPUs. this is a hardware interupt and is handled Because an interrupt will occur on any transition at lBO the by oB2. Because there is just one interrupt for CPU, you user must program the oBs not to respond when the inter- should identify which module issued the interrupt by checking rupts are reset, a transition from 1 to o The OBs should only each of the interrupt information registers of the counter respond when the transition is from 0 to 1. the following modules connected to that cPU. this is done in ob2 of each statements could be installed at the beginning of the ob to CPU. Each counter module may be connected to more than provide interrupt reaction only on ao to 1 transition one interrupt; Le one counter module may be connected to the interrupts of CPU 1 and CPU 2, while another counter AIO.x module is just connected to the interrupts of CPU 2 BEC Note: Jumper Description If the 6Es5 242 module is installed and the group interrupts OB2 89 System interrupt IRA'for CPU 1 are used, an input module cannot be assigned to byte OB2 7-10 System interrupt IRB for CPU 2 address ( B0). If there is an input module installed with byte OB2 6-11 System interrupt IRC for CPU 3 address 0(B0)assigned, the group interrupt will not operate OB2 5-12 System interrupt IRD' for CPU 4 instead, the input module will operate. s5-115u 2.3 Switch $3-System Interrupts The S5-115u has two system interrupts these are hardware interrupts, and are handled by two organization blocks. You Switch S3 provides the module a choice of which system have to specify which modules will be connected to which interrupt it will be connected to within the PC. the 6ES5 242 interrupt, and handle the interrupts via the availavle OBs can be connected to one of seven different interrupt lines For example, If more than one module is connected to IrA' by closing the proper jumper on switch S3. Which interrupt then each of the modules connected must have their infomation is used is dependent on which type of pc the module is Registers read to determine which module issued the interrupt installed in.a brief description of how to handle the interrupts for a particular system is given below OBx Jumper Description NOTE. All Jumpers on switch S3 which do not pertain to the system OB2 89 System interrupt IRA OB being used should be left open. 7-10 System interrupt IRB S5-150 The S5-150 does not use switch S3; instead Group interrupt switch $2 is used to assign interrupts. when using a S5-150 all of the jumpers should be open. Refer to the previous section for interrupt handling with the S5-150 46 Chapter 2 Module Setup Procedures 2.4 Switch S4-Gate Signal Conditioning 2.6 Switch S6- Gate Input Routing Switch S4 is used to change the transition direction of the Switch S6 is used to physically connect the input to each of gate input signals that feed the interrupt system of the the five gate inputs of the AM 9513 to either the external gate 6ES5 242 module. The first three external gate signals, G1-G3 input or the FOUT signal. The external gate input is route are fed to three of the interrupt lines of the AM 9519 interrupt hrough optocoupling from the connectors located on the front controller chip of the module (see section 2.8.1, Plug Connector). The FOUT This allows use of any of the three external gate inputs to signal is an output of the aM 9513 counter chip which can trigger an interrupt for the module. the Interrupt Mask Register be programmed by the user (see section 3, 3 Master Mode must be set accordingly to enable the gate interrupts. Note Register also that the external gate signals are first routed through For example, if you connect the gate control input of counter 1 switch S6 to the Fout signal, and you would like to use the FOUT The AM 9519 interrupt controller chip is firmware programmed signal for an input to counter 2, you would specify counter to aflow ao to 1 transition You must determ which type 1 as the pulse source in the counter mode register of counter 2. of external gate transition will be used (1 to 0 to 1), and set switch S4 accordingly. Gate External Input F2 Scaler〔FoUT 2=20 Jumper Description 1-8 G1 external gate input to AM 9519 234 3-18 4-18 5-16 6-16 2-7 G2 external gate input to AM 9519 7-14 8-14 G3 external gate input to AM 9519 9-12 10-12 4- G4 external gate input, not used Jumper closed =0 to 1 transition, rising edge. Jumper open=1 to o transition, fallIng edge 2.7 Jumper Assignments There are several solder type jumpers which are installed on the 6ES5 242 module, Their meanings are listed below 2.5 Switch S5-Counter Input Routing Jumper Delivery State Description Switch S5 is used to physically connect the input to each f the five counter inputs of the am 9513 to either the external A-B Usedfor testing counter input or the FOUT signal. The external counter Input pen Used to enable de coding of is routed through optocoupling from the connectors located on the front of the module(see section 2.8.1, Plug Connector) E-F closed The FOUT signal is an output of the AM 9513 counter chip Used for module addressing which can be programmed by the user (see section 3.3 in conjunction with swith S1 Master Mode Register G-H Used to determine if the For example, if you connect the counter input of counter 1 to module is a master (open) the FOUt signal and you would like to use the FOUt signal or slave(closed for an input to counter 2, you would specify counter 1 as I-K closed Used to determine if the the pulse source in the counter mode register of counter 2 module is reset with the system CPKL signal Counter External Input F2 Scaler(FOUn Is used to enable(closed) the traP interrupt routine 2-20 stored in firmware for 8085 3-18 4-18 5-16 6-16 8-14 12 10-12 Chapter 2 Module setup Procedures 2.8 Inputs And Outputs 2.8.1 Plug Connectors Plug connector Pinout The connection of the 6ES5 242 counter module to the user inputs and outputs is accomplished via a 9-pin plug connector There are five such connectors mounted on the front plate Pins of the module, one for each of the five counters. see Figures 2-1 and 2-2) 5. Gate Input() Pin Signal Description 8. Gouter ou 刚旧 4. Gate Iput signal Shield Cable shield connection 2 INXM Counter Input x, m terminal (minus) INX Counter Input x, signal. 4 put( Tx Gate input x, sign ExtV呲t(+) TxM Gate Input x, M terminal(minus 1. shield Counter output x, external voltage not connected Pin Plug 8 c er Output x, signal (emale) AxM Counter Output x, external voltage(minus) NOTE:x= 1 Figure 2-2 242 Module plug Connector Pinot Plug Connector Block Diagram 2.8.2 Counter and Gate inpt Plug The counter and gate inputs which are connected through the front connectors of the module are galvanically isolated by means of optocouplers. The input circuitry is identical for both types of inputs and can be configured for Ttl levels or Gate Input 十 24 vdc levels Device The counter inputs are pulse edge sensitive. The gate inputs can be programmed in the counter mode(cm) register to be either pulse edge sensitive or level sensitive 3 Figure 2-3 illustrates the circuitry of the counter input gates Counter Input The circuit is supplied with an input resistor (Rx) to allow Device 2 different input voltage levels to be selected. A capacitor (Cx) can be added to the output to suppress noise spikes. note that the counting frequency is affected when capacitors are Counter Output Device 9 6 1NX O-O Externally Supplied dc Voltage Figure 2-3 Counter& Gate Input circuitry icates Connection for Common ground figure 2-1 242 Module Plug Connector block Diagram Module setip Chapter 2 rocedures TTL Level Specifications 2.8.3 Counter Outputs The input circuit for TIL levels should be designed to provide The output of each of the five counters is routed to the pl a+5 vdc at INX continously, and provide an open collector connectors on the front of the module, these outputs configured circuit at the INxM input, which does the switching galvanically isolated by means of optocouplers. The outputs This circuit configuration is show in Figure 2-4 are the equivalent of p switches and are current limited Driving distance is a function of the external voltage source and, of course, the type of wire used Distances of 200 meters and beyond are attainable, Figure 2-6 illustrates the counter 0^ output circuitry configuration Figure 2-4 Counter Gate Input TTL Level Circuitry Description Figure 2-6 Counter output Circuitry 4.75-525Vde NxM 05-08vdc Low Level INXM 1 ma leakage High Level Description Value current Ax high Level 22v Residual voltage approx. 2V input current approx 6.5 ma INXM=0.4 V INx = 5V output Current -100 ma Input Resistance approx 500 ohm Ax Low Level Resident curent= -100 ua X nper Short Circuit 200ma AxP=24V AXM=0V Rext=0 AXP Extemal supply voltag Switching Freq 10kHz Rext 330 ohm 24 Vdc Level specifications Delay Times Low to High 20 usec Rext 330 oh Figure 2-5 illustrates the necessary configuration for 24 Vinput High to Low 20 usec Rext= 330 ohm to the gate input circuit Rise Time 1 usec Rext= 330 ohm Fall Time 5 usec Rext 330 ohm NOTE: Rext s external load resistance VC 2.8. 4 Signal Conditioning The Cx and Rx numbers for each of the counters and gates are listed belo Figure 2-5 Counter& Gate Input 24 V Level Circuitry Counter/Gate Counter Cx p Gate Cx Rx c15R2 scription alue Notes c16R22 c23R27 INXM 00v c17R23 C24R28 13-33vdc 4 High Level c18R24 c25R29 INX 35-14.5Vdc Low Level C19R25 C26R30 Input current approx, 12 ma INXM=OV, INX=24 Vdc input Resistance approx, 2 k ohm The values for Cx and the maximum counting frequency are 1.5 k ohm listed belo Maximum Counting Freq Cx value app 2000 khz no capacitor installed approx 200 kHz 100pf approx 20 Khz 2 kHz 10 n 49 Chapter 2 Module Setup Procedu 2 9 Module pin out 2.10 6ES5 242 Module Memory Map The 6ES5 242 module is supplied with a 48-pin connector Setting of the physical address of the 6ES5-242 module was which conforms to DIN 41612. The pin out of the module is discussed in an earlier section In that section the subaddress listed below was shown to have 16 possible addresses. This section will map out these 16 subaddresses Pin b Direct reading and writing operations to the module are accomplished through peripheral words ( PWxx). This is +5 y 2468 particulary useful when yau need to develop a custo PESP ADB O CPKL software function See Chapter 4 for detailed information on Standard Software Blocks. Exercise extreme caution when ADB 1 MEMR using this feature with standard software as these two opel 10 ADB 2 MEMW tions may interfere with each other. 12 ADB 3 IRA ADB 4 DB O 16 RB ADB 5 DB 1 Sub Register name Register name 18 IRC ADB 6 DB 2 Address Write Operation Read Operation RD' ADB 7 DB 3 Control Interrupt Information -High IRE' ADB 8 not assigned Interrupt lnformation -Low 24 IRF ADB 9 DB 5 Function Number Error Signal -High ADB 10 DB 6 not assigned ignal-Lo ADB 11 DB 7 Interrupt Mask- High" not assigned PL 4. EANK xxX5 Interrupt Mask-Low* not assigned O V Master Mode- High Result Counter 1-High XXX Master Mode-Low Result Counter 1-Low xx8 Counter Mode- High* Result Counter 2- High xxX Counter Mode -Low Result counter 2-Low XXA Load-High Result Counter 3- high Load- Low Result Counter 3-Low lold- Highi Result Counter 4-High Hold-Low' Result Counter 4-Low E Alarm-H Result Counter 5- High Aiarm -Low' Result Counter 5-Low The value in this register will be sent to any of the counters specified during the parameter assignment. NOTE The Standard software offering does not read the alarm register when parameters are assigned to counters 3, 4, and 5.

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