ADI ADSP-21469：第四代高性能DSP英文产品数据手册.pdfADI ADSP-21469

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详细说明：ADI ADSP-21469：第四代高性能DSP英文产品数据手册pdf,ADI ADSP-21469：第四代高性能DSP英文产品数据手册Preliminary Technical Data ADSP-21462/ADSP21465/ADSP-21467/ADsP21469 TABLE OF CONTENTS Summa Key Features--Processor Core Input/Output Feat Table of contents “++·+ General Description Family Core Architecture emory 6 External me ry 6 Input/Output Features System design Development Tools… Additional Information Pin Function Descriptions 13 Data modes Boot modes 17 Core Instruction rate to clkin ratio modes .18 Operating conditions 18 Electrical Characteristics Maximum power dissipation 20 Absolute Maximum Ratings ESD Sensitivity 20 Timing Specifications…,,…,,.20 Output Drive Currents.....................52 Test Conditions Capacitive Loading………….52 Thermal Characteristics 53 Ball configuration- ADSP-21462W/ADSP-21465W/ ADSP21469W∴ PBGA Pinout-ADSP-21462W/ADSP-21465W/ ADSP-21469W Ba! configuration-ADSP-21467/ADSP21469………57 PBGA Pinout- ADSP-21467/ADSP-21469 58 Outline dimensions Automotive products 61 Ordering guide Rev. PrC Page 3 of 2009 ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Preliminary Technical Data GENERAL DESCRIPTION The ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Table 1. SHARC Family Features( Continued) ShaRC processors are members of the SIMD SHARC family of DSPs that feature Analog Devices' Super Harvard architec- 3 ture. The processors are source code compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x, and ADSP-2116x DSPs as well as with first generation ADSP-2106x SHARC pro cessors in SISD(single-instruction, single-data)mode. These 寸N∽s 9〓e new processors are 32-bit/40-bit floating point processors opti- Feature mized for high performance audio applications with its large IDP Yes on-chip sram, multiple internal buses to eliminate i/o bottle necks, and an innovative digital applications interface(DAl) Serial Ports 8 8 8 8 SRU Table 1. ShaRC Family features DDR2 es Memory Interface UART a DA| and dp20/1420/1420/1420/1420/14 Feature pins pins pIns pIns pIns Frequency 40040 Link ports 2 2 2 450 450 MHZ MHZ MHz MHz MHz S/PDIF Transceive RAM 5M bits 5M bits 5M bits 5M bits 5M bits ROMT N/a 4M bits 4M bits N/A N/A AMI Interface Yes es Yes es Yes with 8-bit Audio No Yes Support Decoders in SPI 2 2 2 2 2 ROM TWI Yes Yes Yes Pulse-Width Yes Ye es Yes Yes Yes Modulation Package 324 324 324 324 324 b S/PDIF es Yes ballball ball Yes PBGAPBGAPBGAPBGA PBGA DTCP Yes Ye es No No No SRO 128dB128dB128dB128dB128dB DDR2 1/2 1/2 1/2 1/2 1/2 Performance Memory CCLK CCLK CCLK CCLK CCLK Interface Max Max Max Max Max Audio decoding algorithms include PCM, Dolby Digilal EX, Dolby ProlugicIIx, DTS 96/24, Neo: 6, DTS ES, MPEG-2 AAC, MP3, and functions like bass DDR2 16 bits 16 bits16 bits 16 bits 16 bits management, delay, speaker equalization, graphic equalization, and more Decoder/post-processor algorithm combination support varies depending Memory Bus upon the chip version and the system configurations. Please visit Widt alog. com for complete informatic The ADSP-21462W and ADSP-21463W processors provide the Digital Trans Direct dma Yes mission Content Protection protocol, a proprietary security protocol.Contact from sports your Analog devices sales office for more information Memory As shown in the functional block diagram on Page 1, the FIR es Ye processor uses two computational units to deliver a significant Accelerator performance increase over the previous SharC processors on a range of DSP algorithms. Fabricated in a state-of-the-art, high Yes Yes Ye Ye speed, CMOS process, the processor achieves an instruction Accelerator ycle time of 2.22 ns at 450 MHz and 2.5 ns at 400 MHz. With FFT es Yes its SIMD computational hardware, the processors can perform Accelerato 2.7 GFLOPS running at 450 MHz and 2.4 GFLOPS running at 400 MHZ MLB Yes 0 Interface Rev. Prc Page 4 of 62 January 2009 Preliminary Technical Data ADSP21462/ADSP-21465/ADSP-21467/ADSP21469 Table 2 shows performance benchmarks for the ADSP-2146x FAMILY CORE ARCHITECTURE processors. The ADSP-2146x is code compatible at the assembly level with Table 2. Processor benchmarks the alsp-2137x ADSP-2136x ADSP-2126x, ADSP-21160 and ADSP-21161, and with the first generation ADSP-2106x Speed SHARC Processors. The ADSP-2146x shares architectural fea Benchmark Algorithm (at 450 MHz) tures with the adsp-2126x, ADsP-2136x ADSP-2137x and 1024 Point Complex FFT(Radix 4, With Reversal)20.44 us ADSP-2116x SIMD SHARC processors, as detailed in the fol- FIR Filter(per Tap) lowing sections 1.11n IIR Filter(per Biquad) 4.43ns SIMD Computational Engine Matrix Multiply(Pipelined The ADSP-2146x contains two computational processing ele 3×3×3×1 10.0ns ments that operate as a single-instruction, multiple-data [4×4]×[4×1 1778ns (SIMD)engine. The processing elements are referred to as PeX Divide(y/×x) 667ns and PEY and each contains an ALU, multiplier, shifter, and reg Inverse square root 10.0ns ister file. Pex is always active and pey may be enabled by setting the peyen mode bit in the model register when this Assumes two files in multichannel simd mode mode is enabled, the same instruction is executed in both pro- The ADSP-2146x continues SHARC's industry-leading stan cessing elements, but each processing element operates on different data. This architecture is efficient at executing math dards of integration for DSPs, combining a high performance intensive DsP algorithms 32-bit DSP core with integrated, on-Chip system features Entering simd mode also has an effect on the way data is trans The block diagram on Page l illustrates the following architec ferred between memory and the processing elements. When in tural features. SIMD mode, twice the data bandwidth is required to sustain Two processing elements, each of which comprises an computational operation in the processing elements. Because of ALU, multiplier, shifter, and data register file this requirement, entering SIMD mode also doubles the band Data address generators(DAGl, DAG2) width between memory and the processing elements. When using the dags to transfer data in SIMd mode two data values Program sequencer with instruction cache are transferred with each access of memory or the register file PM and DM buses capable of supporting four 32-bit data Independent Parallel Computation Units transfers between memory and the core at every core pro cessor cycle Within each processing element is a set of computational unit Two programmable interval timers with external event The computational units consist of an arithmetic/logic unit counter capabilities (ALU), multiplier, and shifter. These units perform all opera tions in a single cycle. The three units within each processing On-chip SRAM element are arranged in parallel, maximizing computational JTAG test access port throughput. Single multifunction instructions execute parallel FFT FIR IIR accelerators ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing ele- The block diagram of the processor on Page l also illustrates the ments. These computation units support IEEE 32-bit single following architectural features precision floating point, 40-bit extended precision floating DMA controller point, and 32-bit fixed-point data formats Digital applications interface that includes four precision Data Register Fill clock generators(PCG), an S/PDIF-compatible digital audio receiver/transmitter with four independent asyn A general-purpose data register file is contained in each pro- cessing element The register files transfer data between the chronous sample rate converters, an input data port(IDP) computation units and the data buses, and store intermediate with eight serial ports, DTCP cipher, eight serial interfaces, a 20-bit parallel input port(PDAP), and a flexible signal results. These 10-port, 32-register16 primary, 16 secondary) outing unit(DAI SRU) register files, combined with the processor's enhanced Harvard architecture allow unconstrained data flow between computa Digital peripheral interface that includes two timers,one tion units and internal memory. The registers in PEX are UART, two serial peripheral interfaces(SPI), a 2-wire referred to as Ro-R15 and in Pey as so-S15 interface (TWI), and a flexible signal routing unit (DPI SRU) Single-Cycle Fetch of Instruction and Four Operands The adsP-2146x features an enhanced Harvard architecture in which the data memory(dm)bus transfers data and the pro m memory(Pm)bus transfers both instructions and data (see Figure 1 on page 1). With the its separate program and data Rev. Prc Page 5 of 62 2009 ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Preliminary Technical Data memory buses and on-chip instruction cache, the processor can UR Accelerator simultaneously fetch four operands (two over each data bus The iir (infinite impulse response) accelerator consists of a and one instruction(from the cache), all in a single cycle 1440 word coefficient memory for storage of biquad coeffi Instruction Cache cients, a data memory for storing the intermediate data and one MAC unit. A controller manages the accelerator. The llr accel- The ADSP-2146x includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four erator runs at the peripheral clock frequency data values. The cache is selective-only the instructions whose MEMORY fetches conflict with pm bus data accesses are cached. This cache allows full speed execution of core, looped operations The aDSP-2146x adds the following architectural features to such as digital filter multiply-accumulates, and fft butterfly the simd sharc family core processing On-Chip Memory Data Address Generators With Zero-Overhead hardware The processors contain 5 Mbits ofinternal RAM. Each block Circular Buffer Support can be configured for different combinations of code and data The ADSP-2146x's two data address generators(DAgs)are storage(see Table 3 on Page 7). Each memory block supports used for indirect addressing and implementing circular data single-cycle, independent accesses by the core processor and i/O processor. The adsp-2146x memory architecture, in combina buffers in hardware. Circular buffers allow efficient program ming of delay lines and other data structures required in digital tion with its separate on-chip buses, allow two data transfers signal processing, and are commonly used in digital filters and trom the core and one from the i/O processor, in a single cycle Fourier transforms. The two DA Gs of the processors contain The processors SRAM can be configured as a maximum of sufficient registers to allow the creation of up to 32 circular buff- 160k words of 32-bit data 320k words of 16-bit data. 1067k ers(16 primary register sets, 16 secondary ). The DAGs words of 48-bit instructions(or 40-bit data), or combinations of automatically handle address pointer wraparound, reduce over different word sizes up to 5 megabit. all of the memory can be head, increase performance, and simplify implementation accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float Circular buffers can start and end at any memory location ing-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. C flexible Instruction Set between the 32-bit floating-point and 16-bit floating-point for- The 48-bit instruction word accommodates a variety of parallel mats is performed in a single instruction. While each memory operations, for concise programming. For example, the block can store combinations of code and data, accesses are ADSP-2146x can conditionally execute a multiply, an add, and a most efficient when one block stores data using the dm bus for subtract in both processing elements while branching and fetch transfers, and the other block stores instructions and data using ing up to four 32-bit values from memory-all in a single the pm bus for transfers instruction Using the DM bus and Pm buses, with one bus dedicated to a Variable instruction Set Architecture memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the previously existing SHARC family of processors, the ADSP. In addition to supporting the standard 48-bit instructions fro The memory map in Table 3 displays the internal memor 2146x support new instructions of 16 and 32 bits in addition to ng 48 bit instructions. This feature, called variable address space of the ADSP-21465W and ADSP-21467 proces Instruction Set Architecture(VISA), is based on dropping sors. The memory map in Table 4 displays the internal memory address space of the ADSP-21462W, ADSP-21469 and ADSP redundant/unused bits within the 48-bit instruction to create 21469W processors more efficient and compact code The program sequencer will now support fetching these 16-bit and 32-bit instructions as well The 48-bit space section describes what this address range looks in addition to the standard 48-bit instructions both from inter- like to an instruction that retrieves 48-bit memory nal as well as external memory Source modules will need to be The 32-bit section describes what this address range looks like built using the VISA option, in order to allow code generation to an instruction that retrieves 32-bit memory tools to create these more efficient opcodes EXTERNAL MEMORY FFT Accelerator The external port on the ADSP-2146x SHaRC provides a high FFT accelerator implements radix- 2 complex/real input, com performance, glueless interface to a wide variety ofindustry plex output FFT with no core intervention standard memory devices. The external port may be used to FIR Accelerator interface to synchronous and/or asynchronous memory devices through the use of its separate internal DDR2 memory control- The FiR (finite impulse response) accelerator consists of a 1024 ler. The 16-bit DDR2 DRAM controller connects to industry word coefficient memory, a 1024 word deep delay line for the standard synchronous DRAM devices, while the second 8-bit data, and four MAC units. a controller manages the accelerator asynchronous memory controller is intended to interface to a The FIR accelerator runs at the peripheral clock frequency variety of memory devices. Four memory select pins enable up Rev. Prc Page 6 of 62 January 2009 Preliminary Technical Data ADSP21462/ADSP-21465/ADSP-21467/ADSP21469 to four separate devices to coexist, supporting any desired com and data storage. With external execution, programs run at bination of synchronous and asynchronous device types. Non slower speeds since 48-bit instructions are fetched in parts from DDR2 DRAM external memory address space is shown in a 16-bit external bus coupled with the inherent latency of fetch Table 5 ing instructions from DDR2 DRAM. VISA mode and simd External Memory Execution mode accesses are supported for DDR2 space In the ADSP-2146x, the program sequencer can execute code directly from external memory bank 0 (SRAM, as well as DDR2 DRAM). This allows more options to a user in terms of code Table 3. ADSP-21465W/ADSP-21467 Internal Memory Space lOP Registers 0x0000 0000-0x0003 FFFF Extended Precision normal or Long Word(64 bits) Instruction Word (48 bits) Normal Word (32 bits) Short Word (16 bits) BLOCKO ROM BLOCKO ROM BLOCK O ROM BLOCK O ROM 0x00040000-0x00047FFF 000080000-0x0008AAA9 0x00080000-0×0008FFFF 0x00100000-00011FFFF Reserved Reserved Reserved Reserved 000048000-0×00048FF0×00090000-0×0001FFF 0x00090000-0×00091FFF 0x00120000-0X00123FFF BLOCK O RAM BLOCK O RAM BLOCKO RAM BLOCKO RAM 0x00049000-0X0004EFFF 0x0008C0000X00093FFF 0x00092000-0×0009DFFF 0x001240000X0013BFFF Reserved Reserved Reserved Reserved 0x0004F0000x0004FFFF 0x0009E0000x0009FFFF 0x0009E000-0x0009FFFF 0x0013C000-0x0013FFF BLOCK 1 ROM BLOCK 1 ROM BLOCK 1 ROM BLOCK 1 ROM 0x0050000x00057FF0×000A0000x0AA90x000A0000×000AFFF 0x00140000-0X0015FFFF Reserved Reserved Reserved Reserved 0x00058000-0x00058FFF 0x000B000-0x000B1FFF 0x000B0000-0X000B1FFF 0x00160000-000163FFF BLOCK 1 RAM BLOCK 1 RAM BLOCK 1 RAM BLOCK 1 RAM 0x00059000-0×0005EFFF 0x000AC0000×000B3FFF 0×000B2000-0x000 B DFFF 0×00164000-0×0017BFFF Reserved Reserved Reserved Reserved 0×0005F000×00550×00E000×0008FFF5 0x000BE0000×000 B FFFF 0x0017C000-0X0017FFFF BlOCK 2 RAM BLOCK 2 RAM BLOCK 2 RAM BLOCK 2 RAM 0×00060000x0063F0×00c000×000c554 0x000C0000-0x000C7FFF 0x00180000-0x0018FFFF Re 0x00064000x0006FFF5|0x00oC8000-0x000FFF 0x000C8000-0×000 D EFFF 0x00190000-0X001 B EFFF blOCK 3 RAM BLOCK 3 RAM BLOCK 3 RAM BLOCK 3 RAM 0x00070000-0X00073FFF 0x000E00000X000E5554 0x000E0000-0X000E7FFF 0x001C0000-0X001 C FFFF Reserved Reserved Reserved Reserved 0x00074000-0X0007FFFF 0000E8000-0x000 F FFFF 0x000E8000-0x000 FFFFF 0x001D0000-0x001FFFF Rev. PrC Page 7 of 62 2009 ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Preliminary Technical Data Table 4. ADSP-21462W/ADSP-21469/ADSP-21469W Internal Memory Space lOP Registers 0X0000 0000-0X0003 FFF Extended Precision normal or Long Word (64 bits) Instruction Word (48 bits) Normal Word 32 bits) Short Word (16 bits) BLOCK O RAM BLOCK O RAM BLOCKO RAM BLOCKO RAM 0x00049000-0×0004EFFF 0x0008C000-0x00093FFF 0x00092000-0X0009DFFF 0x001240000×0013BFFF Reserved Reserved Reserved Reserved 0x0004F0000×00058FFF 0x0009E0000x000B1FFF 0x0009E000-0X000B1FFF 0x0013C000-0×00163FFF BLOCK 1 RAM BLOCK 1 RAM BLOCK 1 RAM BLOCK 1 RAM 0x00059000-0x0005EFFF 0x000AC000-0x000B3FFF 0x000B20000x000 B DFFF 0x00164000-0X0017BFFF eserved Reserved Reserved R eserved 0x0005F000-0X0005FFFF 0XO0OB E000-0X000B FFFF OXOO0B E000-0XO00B FFFF 0x0017C000-0X0017FFFF BLOCK 2 RAM BLOCK 2 RAM BLOCK 2 RAM BLOCK 2 RAM 0X00060000-0x00063FFF 0x000C0000-0X000C5554 0x000C0000-0X000C7FFF 0x00180000-0x0018FFFF Reserved Reserved Reserved Reserved 0x000640000×0006FFFF 0x000C8000-0x000 D FFFF 0x000C8000-0x000 DEFFF 0x001900000×001 B EFFE BLOCK 3 RAM BLOCK 3 RAM BLOCK 3 RAM BLOCK 3 RAM 0x000700000×00073FFF 0x00OE00000X000E5554 0x000E00000X000E7FFF 0x001C00000x001 CFFFF Reserved Reserved Reserved Reserved 0x00074000-0×0007FFFF 0x000E8000-0x000 FFFFF 0x000E8000-0x000 F FFFF 0x001D0000-0x001 F FFFF DDR2 Support Table 6. External Memory for DDR2 DRAM Addresses The ADSP-2146x supports a 16-bit DDR2 interface operating at a maximum frequency of half the core clock. Execution from Size in external memory is supported. External memory devices up to 2 Bank Words Address Range Gbits in size can be supported. Delay line DMa functionality Bank o 62M 0x00200000-0X03 FFFFFF supported Bank 1 64M 0x04000000-0x07 FF FFFF DDR2 DRAM Controller Bank 2 64M Ox08000000-OXOBFF FFFF The DDR2 DRAM controller provides an 16-bit interface to up Bank 3 64M OxOC00 0000-OXOFFF FFFF to four separate banks of industry-standard DDR2 DRAM devices. Fully compliant with the ddr2 draM standard, each bank can has its own memory select line(DDR2_CS3- Note that the external memory bank addresses shown are for DDR2_CSO), and can be configured to contain between 32M normal-word(32-bit)accesses. If 48-bit instructions as well as bytes and 256M bytes of memory DDR2 DRAM external mem 32-bit data are both placed in the same external memory bank, ory address space is shown in Table 6 care must be taken while mapping them to avoid overlap. In case of 32-bit wide external memory two 48-bit instructions A set of programmable timing parameters is available to config will be stored in three 32-bit wide memory locations. For exam ure the DDR2 DRAM banks to support memory devices ple, if 2k instructions are placed in 32-bit wide external memory starting at the bank 0 normal-word base address 0x0030 0000 Table 5. External memory for Non DDR2 DRAM Addresses (corresponding to instruction address 0x0020 0000 )and ending at address 0x0030 OBFF(corresponding to instruction address Size in 0x0020 07FF), then data buffers can be placed starting at an Bank Words Address Range ddress that is offset by 3k 32-bit words (for example, starting at Bank o 14M 0x00200000-0x00 FFFFFF 0x00300C00) Bank 1 16M 0x04000000-0X04 FF FFFF Asynchronous Memory Controller Bank 2 16M 0x08000000-0x08 FF FFFF The asynchronous memory controller provides a configurable interface for up to four separate banks of memory or I/O Bank 3 16M OxOC00 0000-OXOCFF FFFF devices. Each bank can be independently programmed with dif- ferent timing parameters, enabling connection to a wide variety of memory devices including SRAM, flash, and EPROM, as well as I/0 devices that interface with standard memory control Rev. Prc Page 8 of 62 January 2009 Preliminary Technical Data ADSP21462/ADSP-21465/ADSP-21467/ADSP21469 lines. Bank 0 occupies a 14M word window and banks 1, 2, and Delay Line DMa 3 occupy a 16M word window in the processor's address space but, if not fully populated, these windows are not made contigo The ADSP-2146x processor provides delay line DMA function ality This allows processor reads and writes to external del ous by the memory controller logic line buffers(and hence to external memory) with limited core The asynchronous memory controller is capable of a maximum interaction throughput of TBD Mbps using a TBD MHz. external bus speed Other features include 8 to 32-bit packing and unpacking, boot Scatter/Gather DMa ing from bank select l, and support for delay line DMa The ADsP-2146x processor provides scatter/gather DMA functionality INPUT/OUTPUT FEATURES This allows processor DMA reads/writes to/from non-contin The adsp-21462W, ADSP-21465W and ADSP-21469W1/O geous memory blocks processors provide 67 channels of DMA, while ADSP-21467 and adsP-21469 1/0 processors provide 36 channels of DMa Digital Applications Interface(DAl) as well as an extensive set of peripherals. These include a 20 lead The digital applications interface(DAi) provides the ability to digital applications interface, which controls connect various peripherals to any of the dai pins Eight serial ports (DALP20-1) S/PDIF receiver/transmitter Programs make these connections using the signal routing unit Four precision clock generators (SRU), Shown in Figure 1 Input data port/parallel data acquisition port The sru is a matrix routing unit (or group of multiplexers)that enables the peripherals provided by the Dal to be intercon Four asynchronous sample rate converters nected under software control. This allows easy use of the dai The ADSP-2146x processor also contains a 14 lead digital associated peripherals for a much wider variety of applications peripheral interface, which controls by using a larger set of algorithms than is possible with noncon Two general-purpose timers igurable signal paths Two serial peripheral interfaces The Dai also includes eight serial ports, four precision clock generators(PCG),S/PDIF transceiver, four ASRCs, and an One universal asynchronous receiver/transmitter Uart) input data port(IDP). The IDP provides an additional input An I2CB-compatible 2-wire interface path to the sharc core, configurable as either eight channels of serial data, or a single 20-bit wide synchronous parallel data Two PCGs(C and d) can also be routed through dpl acquisition port. Each data channel has its own DMa channel DMA Controller that is independent from the processors serial ports The processors on-chip dMa controller allows data transfers Serial ports without processor intervention. The DMA controller operates The ADSP-2146x features eight synchronous serial ports that independently and invisibly to the processor core, allowing provide an inexpensive interface to a wide variety of digital and DMA operations to occur while the core is simultaneously exe- mixed-signal peripheral devices such as Analog Devices cuting its program instructions. DMA transfers can occur between the ADSP-2146x's internal memory and its serial ports AD183x family of audio codecs, ADCs, and DACs. The serial the SPI-compatible(serial peripheral interface)ports, the IDP ports are made up of two data lines, a clock, and frame sync. The data lines can be programmed to either transmit or receive and (input data port), the parallel data acquisition port(PDAp)or each data line has a dedicated dma channel the uart Serial ports can support up to 16 transmit or 16 receive channels Sixty-seven channels of DMa are available on the ADSP-21462W, ADSP-21465W and ADSP-21469w devices of audio data when all eight SPORTs are enabled, or four full duplex tDM streams of 128 channels per frame and thirty-six channels on the adsP-21467 and ADSP-2146 The breakdown is as follows: 16 via the serial ports, eight via the The serial ports operate at a maximum data rate of 56. 25 Mbps input data port, two for the UARt, two for the SPI interface, Serial port data can be automatically transferred to and from two for the external port, two for dtCP (or memory-to-mem on-chip memory external memory via dedicated DMa chan ory data transfer when DTCP is not used), two for the link port nels. Each of the serial ports can work in conjunction with two for the FFt/Fir/iiR accelerators, and up to 3 1 dMa chan another serial port to provide TDM support. One SPOrt pro nels for the media local bus interface on the aDsp-21462W vides two transmit signals while the other SPort provides the ADSP-21465W and adsp-21469W two receive signals. The frame sync and clock are shared Programs can be downloaded to the adsp-2146x using dma Serial ports operate in five modes transfers. Other dma features include interrupt generation Standard DSP serial mode upon completion of DMA transfers, and DMa chaining for automatic linked DMa transfers Multichannel (TDM)mode mode Rev. Prc Page 9 of 62 January 2009 ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Preliminary Technical Data Packed i2s mode scrambling system) will be protected by this copy protection Left-justified mode system. This feature is available on the ADSP-21462W and ADSP-21465W processors only. Licensing through Dtla is Left-justified mode is a mode where in each frame sync cycle requiredfortheseproductsVisitwww.dtcp.comformore two samples of data are transmitted/received-one sample on information the high segment of the frame synC, the other on the low seg ment of the frame sync Programs have control over various Digital Peripheral Interface(DPl) attributes of this mode The digital peripheral interface provides connections to two Each of the serial ports supports the left-justified and I"S proto serial peripheral interface ports(SPI), one universal asynchro cols(I-s is an industry-standard interface commonly used by nous receiver-transmitter (Uart), 12 flagS, a 2-wire interface audio codecs, ADCS, and DACS such as the analog Devices (TWT), and two general-purpose timers AD183x family), with two data pins, allowing four left-justified or I-s channels(using two stereo devices)per serial port, with a Serial Peripheral( Compatible)Interface maximum of up to 32I'S channels. The serial ports permit lit The ADSP-2146x SHARC processors contain two serial periph tle-endian or big-cndian transmission formats and word lengths eral interface ports(SPIs). The SPI is an industry-standard selectable from 3 bits to 32 bits. For the left-justified and IS synchronous serial link, enabling the SPI-compatible port to modes, data-word lengths are selectable between 8 bits and 32 communicate with other SPi compatible devices The sPi con- bits Serial ports offer selectable synchronization and transmit sists of two data pins, one device select pin, and one clock pin. It modes as well as optional u-law or A-law companding selection is a full-duplex synchronous serial interface, supporting both on a per channel basis. Serial port clocks and frame syncs can be master and slave modes. The SPi port can operate in a multi internally or externally generated master environment by interfacing with up to four other SPI The serial ports also contain frame sync error detection logic compatible devices, either acting as a master or slave device. The where the serial ports detect frame syncs that arrive early(for SPI-compatible peripheral implementation also features pro- example frame syncs that arrive while the transmission/recep grammable baud rate and clock phase and polarities. The SPI tion of the previous word is occurring). All the serial ports also compatible port uses open drain drivers to support a multimas share one dedicated error interrupt ter configuration and to avoid data contention S/PDIF-Compatible digital Audio Receiver/Transmitter UART Port and Synchronous/Asynchronous Sample Rate Converter The processors provide a full-duplex universal asynchronous The S/PDIF receiver/transmitter has no separate DMA chan Receiver/Transmitter qUART) port, which is fully compatible nels. It receives audio data in serial format and converts it into a with PC-standard UARTs. The UART port provides a simpli- biphase encoded signal. The serial data input to the fied UART interface to other peripherals or hosts, supporting receiver/transmitter can be formatted as left justified, IlS or full-duplex, DMA-Supported, asynchronous transfers of serial right justified with word widths of 16, 18, 20, or 24 bits data The uart also has multiprocessor communication capa bility using 9-bit address detection this allows it to be used in The serial data, clock, and frame sync inputs to the S/PDIF multidrop networks through the rs-485 data interface stan- receiver/transmitter are routed through the signal routing unit dard. The UART port also includes support for 5 to 8 data bits, 1 (SRU. They can come from a variety of sources such as the or 2 stop bits, and none, even, or odd parity. The UART port SPORTS, external pins, the precision clock generators(PCgs), supports two modes of operation and are controlled by the sru control registers PIO (programmed I/0)-The processor sends or receives The sample rate converter(Asrc) contains four asrc block data by writing or reading I/O-mapped UART registers and is the same core as that used in the adi896 192 khz stereo The data is double-buffered on both transmit and receive asynchronous sample rate converter and provides up to 128 dB SNR. The asrC block is used to perform synchronous or asyn DMA(direct memory access)-The DMA controller trans chronous sample rate conversion across independent stereo fers both transmit and receive data. This reduces the channels, without using internal processor resources. The four number and frequency of interrupts required to transfer SRC blocks can also be configured to operate together to data to and from memory The uart has two dedicated convert multichannel audio data without phase mismatches DMA channels. one for transmit and one for receive. These Finally, the aSrC can be used to clean up audio data from jit dMa channels have lower default priority than most Dma tery clock sources such as the S/PDiF receiver channels because of their relatively low service rates Digital Transmission Content Protection The UarT port,'s baud rate, serial data format, error code gen eration and status, and interrupts are programmable The DTCP specification defines a cryptographic protocol for Supporting bit rates ranging from(fpcLr/ 1,048, 576)to protecting audio entertainment content from illegal copying, (f pCLK/16)bits per second intercepting, and tampering as it traverses high performance digital buses, such as the IEEE 1394 standard. Only legitimate entertainment content delivered to a source device via another approved copy protection system(such as the DVD content Rev. Prc Page 10 of 62 January 2

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