FUJITSU SPI接口存储芯片MB85RS64 系列英文资料.pdfFUJITSU SPI接口存

文件名称: FUJITSU SPI接口存储芯片MB85RS64 系列英文资料.pdf

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详细说明：FUJITSU SPI接口存储芯片MB85RS64 系列英文资料pdf,FUJITSU SPI接口存储芯片MB85RS64 系列英文资料Shandong C he weishi co, Ltd PRELIMINARY MB85RS64A ■ BLOCK DIAGRAM Serial-Parallel Converter 8 FRAM Cell array 8,192×8 CS FRAM SCK Status Register HOLD O Column Decoder/Sense Amp/ Write Amp WP Data register SO O Paralle -Serial Converter FUITSU Shandong C he weishi co, Ltd MB85RS64A PRELIMINARY ■ SPI MODE MB85RS64A corresponds to the SPI mode O (CPOL-0, CPHA-0), and SPI mode 3(CPOL=1, CPHA-1) SCK 6 4 MSB LSB SPI Mode o SCK 6 MSB LSB SPI Mode 3 FUITSU Shandong C he weishi co, Ltd PRELIMINARY MB85RS64A SERIAL PERIPHERAL INTERFACE (SPI) MB85RS64A works as a slave of SPl. More than 2 devices can be connected by using microcontroller equipped with SPI port. By using a microcontroller not equipped with SPI port, SI and so can be bus connected to use. SCK MOSI MISO SO SI SCK SO SI SCK MB85RS64A MB85RS64A Microcontroller CS HOLD CS HOLD SS1 SS2 HOLD1 H OLD2 MOSI: Master Out Slave In MISO. Master In slave out ss, Slave select stem Configuration with sPl Port SO SI SCK Microcontroller MB85RS64A CS HOLD System Configuration without sPl Port FUITSU Shandong C he weishi co, Ltd MB85RS64A PRELIMINARY STATUS REGISTER Bit no Bit name Function Status Register Write Protect This is a bit composed of nonvolatile memories(FRAM). WPEN is related WPEN o WP input to protect writing to a status register (refer to" WRITING PROTECT). Writing with the WrSr command and reading with the RDSR command are possible. Not used bits 6 to 4 These are bits composed of nonvolatile memories, writing with the WrSr command is possible, and 000"is written before shipment. These bits are not used but they are read with the Rdsa command 3 BP1 Block protect This is a bit composed of nonvolatile memory(FRAM). This defines block size for writing protect with the WRITE command(refer to BLOCK BPO PROTECT"). Writing with the WRSR command and reading with the RDSR command are possible Write enable latch This indicates FRAM memory and status register are writable. The WREN command is for setting, and the Wrdi command is for resetting. With the RDSR command, reading is possible but writing is not possible with the WEL WRSR command. WEL is reset after the following operations The time when power Is up The time when the WRDI command is input The time when the WRSR command is input The time when the Write command is input 0 0 This is a bit fixed to o I OP-CODE MB85RS64A accepts 6 kinds of command specified in op-code. Op-code is a code composed of 8 bits shown in the table below. When invalid codes other than codes below are input, they are ignored. If CS is risen while inputting op-code, the command are not performed Name Description Op-code WREN Set write enable latch 00000110 WRD Reset write enable latch 00000100a RDSR Read Status Register 00000101B WRSR Write Status Register 00000001日 READ Read Memory Code 00000011B WRITE Write Memory Code 00000010 FUITSU Shandong C he weishi co, Ltd PRELIMINARY MB85RS64A ■ COMMAND ●WREN The WREN command sets WEL (Write Enable Latch).WEL has to be set with the Wren command before writing operation(WRSR command and WRITE command) CS 4 5 7 SCK alid 0 0 0 0 Invalid High-Z SO WRDI The WRDI command resets WEL (Write Enable Latch). Writing operation(WRITE command and WRSR command) are not performed when WeL is reset 5 SCK Invalid 0 0 0 0 Invalid SO High-Z FUITSU Shandong C he weishi co, Ltd MB85RS64A PRELIMINARY e DSR The rDsr command reads status register data. After op-code of RDSR is input to sl, 8-cycle clock is input to SCK. The SI value is invalid for this time. So is output synchronously to a falling edge of ScK continuously reading status register is enabled by keep on sending SCK before rising CS with the RDSR command 45670 234567 SCK 00000/10 Invalid Data out SO MSB LSB e WRSR The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR op-code to a sl pin, 8 bits writing data is input. WEL (Write Enable Latch) is not able to be written with WRSR command. a sI value correspondent to bit 1 is ignored. Bit o of the status register is fixed to "o"and cannot be written The si value corresponding to bit o is ignored SCK 几几几L Instruction Data In 0000000/1\765 2\10 MSB LSB High-Z FUITSU Shandong C he weishi co, Ltd PRELIMINARY MB85RS64A READ The read command reads FRAM memory cell array data. Arbitrary 16 bits address and op-code of READ are input to sI the most significant address bit is invalid. then 8-cycle clock is input to sCK. so is output synchronously to the falling edge of SCK. While reading the sl value is invalid. When CS is risen, the REAd command is completed, but keep on reading address with automatic increment is enabled by continuously sending clock for 8 cycles each to SCK before Cs is risen. When it reaches the most significant address, it rolls over to come back to the starting address, and reading cycle keeps on infinitely. 34 8910111213181920212223242526272829 SCK OP-CODE 16-bit Address 000000 /11XXxxX12 110. 5x4321oX Invalid MSB SB MSB Data out LSB High-Z SO ●WRTE The WRITE command writes data to FRAM memory cell array. WRITE op-code, arbitrary 16 bits of address and 8 bits of writing data are input to Sl. The most significant address bit is invalid. When 8 bits of writing data is input, data is written to FRAM memory cell array Risen CS will terminate the WRITE command, but if you continue sending the writing data for 8 bits each before CS is risen, it is possible to continue writing vith automatic address increment. when it reaches the most significant address, it rolls over, comes back to the starting address, and writing cycle can be continued infinitely 0 23456 8910111213 181920212223242526272829303 SCK 几 OP-CODE 6-bit Address Data In 000000 1oxxx(2x1)10…54Xa21XX6X5X43X2X①oX MSB LSB MSB LSB High-Z SO FUITSU Shandong C he weishi co, Ltd MB85RS64A PRELIMINARY ■ BLOCK PROTECT Writing protect block is configured by the WRITE command with BP1, BPO value of the status register BP1 BPO Protected block 0 None 0 1800H to 1 FFFH(upper 1/4 0 1000H to 1 FFFH(upper 1/2) 000OH to 1 FFFH(all) ■WR| TING PROTECT Writing operation of the WRITE command and the WrSr command are protected with the value of WEL, WPEN, WP as shown in the table WEL WPEN WP Protected Blocks Unprotected Blocks Status Register Protected Protected Protected 0 Protected Unprotected Unprotected 0 Protected Unprotected Protected Protected Unprotected Unprotected ■ HOLD OPERATION Hold status is retained without aborting a command if HOLd is"L" while Cs is"L". The timing for starting and ending hold status depends on the sck to be"H or L when a Hold pin input is transited as shown in the diagram below. Arbitrary command operation is interrupted in hold status, SCK and sI inputs become don't care And, so becomes High-Z while reading command( RDSR, READ). If Cs is risen with hold status a command is aborted and device is reset SCK uuulluul HOLD Hold condition Hold Condition 0 FUITSU

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