Intel® 64 and IA-32 Architectures Volume 3 System

文件名称: Intel® 64 and IA-32 Architectures Volume 3 System Programming Guide.pdf

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详细说明：英特尔64和IA-32建筑软件开发人员手册，第3A卷：系统编程指南，第1部分(订单编号253668)，英特尔64和IA-32建筑软件开发人员手册，第3B卷：系统编程指南，第2部分(订单编号253669)，英特尔64和IA-32建筑软件开发人员手册，第3C卷：系统编程指南，第3部分(订单编号326019)，以及Intel 64和IA-32架构软件开发人员手册，卷3D：系统编程指南，第4部分(订单编号332831)是描述Intel 64和IA-32体系结构处理器的体系结构和编程环境的集合的一部分。CONTENTS PAGE CHAPTER 1 ABOUT THIS MANUAL ITEL 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL 2 OVERVIEW OF THE SYSTEM PROGRAMMING GUIDE NOTATIONAL CONVENTIONS 1.3.1 Bit and Byte Or 3.2 Reserved Bits and Sottware Compatibility 13.3 Instruction Operand 3.4 Hexadecimal and binary Numbers 13.5 Segmented Addressing 1-8 36 Syntax for CPUID, CR, and msr values 能1盖着1重 3.7 Exceptions 14 RELATED LITERATURE 1-10 CHAPTER 2 SYSTEM ARCHITECTURE OVERVIEW 2.1 OVERVIEW OF THE SYSTEM-LEVEL ARCHITECTURE ·:::.· 2.1.1 Global and Local Descriptor Tables..,..,.......,. 2.1.1.1 Global and local descriptor tables in iA-32e Mode 24 2.1.2 System Segments, Segment Descriptors, and Gates 2.1.2.1 Gates in lA-32e Mode 2-4 2.1.3 Task-state segments and task gates 2.1.3.1 Task-state segments in IA-32e Mode 2-5 2.14 Interrupt and Exception Handling 11 2.14. Interrupt and exception handling iA-32e Mode 5 2.15 Memory Management..,....... ::.:::·::.:::: .:.:: 2.15 Memory Management in iA-32e Mode ......,.,.,.,. 2-6 2.1.6 System Registers. ,,,2-6 2.1.6.1 System Registers in IA-32e Mode 2-7 2.17 Other System Resources 22 MODES OF OPERATION 22.1 Extended Feature Enable register. 23 SYSTEM FLAGS AND FIELDS IN THE EFLAGS REGISTER 2.3.1 System Flags and Fields in IA-32e Mode .2-11 24 MEMORY-MANAGEMENT REGISTERS 24.1 Global Descriptor Table Register(GDTR 2-12 242 Local Descriptor Table Register (LDTR 2-12 24.3 IDTR Interrupt Descriptor Table register 2-12 244 Task Register (TR) 2-13 25 CONTROL REGISTERS 11看 2-13 25.1 CPUID Qualitication of Control register Flags 2.6 EXTENDED CONTROL REGISTERS (INCLUDING XCRO................... 2-19 2.7 PROTECTION KEY RIGHTS REGISTER(PKRU) ,2-21 28 SYSTEM INSTRUCTION SUMMARY 2-21 28.1 oading and Storing System Registers 2-23 282 Verifying of Access Privileges 2-23 28.3 Loading and storing Debug Registers .2-24 284 Invalidating Caches and tlBs ...2-24 28.5 Controlling the processor 2-25 286 Reading performance- Monitoring and Time-Stamp Counters 2-25 286.1 Reading Counters in 64-Bit Mode n着1, 2-26 287 Reading and writing model-Specific Registers 2-26 28.7 Reading and writing Model- Specific Registers in 64-Bit Mode 2-26 288 Enabling processor Extended states...,..........,.. 鲁着 2-26 ∨ol.3AⅢ CONTENTS PAGE CHAPTER 3 PROTECTED-MODE MEMORY MANAGEMENT 3.1 MEMORY MANAGEMENT OVERVIEW 3.2 USING SEGMENTS 3-2 3.2. Basic Flat model 3.2.2 Protected flat mode 3.2.3 Multi-Segment Model 3-4 3.24 Segmentation in lA- 32e mod 3-5 3.25 Paging and segmentation 3-5 33 PHYSICAL ADDRESS SPACE 11着着1 3-6 33.1 Intel 64 Processors and physical Address space 3-6 3.4 LOGICAL AND LINEAR ADDRESSES 3-6 34.1 Logical Address Translation in IA-32e Mode 34.2 Segment Selectors… 11 34.3 Segment registers ,3-8 344 Segment Loading Instructions in IA-32e Mode 345 Segment Descriptors. 11重 3.4.5.1 Code-and Data-Segment Descriptor T ypes 3-12 3,5 SYSTEM DESCRIPTOR TYPES 3-13 3.5.1 Segment descriptor Tables 3-14 3.52 Segment descriptor Tables in IA-32e Mode 3-16 CHAPTER 4 PAGING PAGING MODES AND CONTROL BITS Three paging modes.,.,.,.. 4-1 4.1.2 Paging-Mode Enabling 4-3 4.1.3 Paging -Mode modifiers.... ,4-4 4.1.4 Enumeration of Paging Features by CPUID 4-5 42 HIERARCHICAL PAGING STRUCTURES: AN OVERVIEW ,4-6 43 32-BIT PAGING ,康 4-7 44 PAE PAGING ,4-13 4.4.1 PDPTE Registers 1看 4-13 44.2 Linear-Address Translation with PAE Paging ∴.4-14 4.5 4-LEVEL PAGING .4-19 4.6 ACCESS RIGHTS :..::.::.:.::.:::::::.:: 4-28 46.1 Determination of Access Rights 4-29 46.2 Protection Keys 着鲁着,1,1着1.鲁,重 4-31 4.7 PAGE-FAULT EXCEP TIONS …4-31 4.8 ACCESSED AND DIRTY FLAGS 4-33 9 PAGING AND MEMORY TYPING 4-34 49.1 Paging and Memory typing When the pat is Not Supported (Pentium Pro and pentium ll Processors) 492 Paging and Memory Typing When the Pat is Supported(Pentium Ill and More Recent Processor Familes).",,,..4-34 4-34 493 Caching Paging-Related Information about Memory Typing 4-35 4.10 CACHING TRANSLATION INFORMATION 4-35 4.10.1 Process-Context Identifiers(PCIDs ·· 4-35 4.102 Translation Lookaside Buffers ( tlbs) .4-36 4.102.1 Page Numbers, Page Frames, and Page offsets ,4-36 4.102.2 Caching Translations in TLBS 4-37 4.102.3 Details of tlb use .::.:: 4-37 4.10.2.4 Global Pages 4-38 4.103 Paging-Structure Caches 4-38 4.10.3.1 Caches for Paging structures 4-38 4.103.2 Using the Paging-Structure Caches to Translate Linear Addresses 4-40 4.10.33 Multiple Cached Entries for a Single Paging-Structure Entry ,,4-41 4.10.4 Invalidation of TLBs and Paging-Structure Caches 4-41 4.104.1 Operations that Invalidate TLBs and Paging-Structure Caches 4-41 4.10.4.2 Recommended invalidation 4-43 4.104.3 Optional Invalidation .·:···:·“:· ::·· .4-44 4.10.4.4 Delayed Invalidation 4-45 4.10.5 Propagation of Paging-Structure Changes to Multiple Processors 4-46 4.11 INTERACTIONS WITH VIRTUAL-MACHINE EXTENSIONS (UMX 4-47 4.11.1 VMX Transitions 4-47 ⅣVo.3A CONTENTS PAGE 4.11.2 VMX Support for Address Translation. ................. ,,,,4-47 4.12 USING PAGING FOR VIRTUAL MEMORY ,4-47 4.13 MAPPING SEGMENTS TO PAGES 4-48 CHAPTER 5 PROTECTION 5.1 ENABLING AND DISABLING SEGMENT AND PAGE PROTECTION 5.2 FIELDS AND FLAGS USED FOR SEGMENT-LEVEL AND PAGE-LEVEL PROTECTION 5.2.1 Code- Segment Descriptor in 64-bit Mode 1着道 5-3 53 LIMIT CHECKING 53.1 Limit Checking in 64-bit M 5.4 TYPE CHECKING 着·1,日4 54.1 Null Segment selector Checking :::::.:::...::::::.:....::::::.:...::: 54.1.1 NULL Segment checking in 64-bit Mod PRIVILEGE LEVELS 5.6 PRIVILEGE LEVEL CHECKING WHEN ACCESSING DATA SEGMENTS 5-8 56.1 Accessing Data in Code segments....... 5-9 5.7 PRIVILEGE LEVEL CHECKING WHEN LOADING THE SS REGISTER 5-10 58 PRIVILEGE LEVEL CHECKING WHEN TRANSFERRING PROGRAM CONTROL BETWEEN CODE SEGMENTS 5-10 58.1 Direct Calls or Jumps to Code segments 5-10 58.1.1 Accessing Nonconforming Code Segments 58.1.2 Accessing Conforming Code segments 1 5-12 58.2 Gate Descriptors∵ 5-13 58.3 Call gates 5-13 58.3.1 lA-32e Mode call gates ,5-14 584 Accessing a Code segment through a call gate 1 5-15 58.5 Stack Switching… 5-17 585.1 Stack Switching in 64-bit Mode 5-19 58.6 Returning from a called Procedure............... 5-20 58.7 Performing Fast Calls to System Procedures with the SYSENTER and SYSEXIT Instructions...........5-20 58.7.1 SYSENTER and syseXit Instructions in iA-32e Mode 588 Fast System Calls in 64-Bit Mode 5-22 59 PRIVILEGED INS TRUCTIONS 23 5.10 POINTER VALIDATION ∴5-24 5.10.1 Checking Access Rights(LAR Instruction) ,5-24 5.10.2 Checking Read/Write Rights (VERR and vERW Instructions 1,111看面 ,5-25 5. 10.3 Checking That the pointer offset Is Within limits(LSL Instruction .5-25 5. 10.4 Checking Caller Access Privileges ( 5.10.5 Checking Alignment 5-27 5.11 PAGE-LEVEL PROTECTION 5.11.1 Page-Protection Flags..... 5-28 5.11.2 Restricting Addressable domain 1着1,11着1 ,5-28 5.11.3 Page Type 5-28 5. 11.4 Combining Protection of Both Levels of Page Tables 5.11.5 Overrides to Page Protection 5-29 5.12 COMBINING PAGE AND SEGMENT PROTECTION ...5-29 5.13 PAGE-LEVEL PROTECTION AND EXECUTE-DISABLE BIT .5-30 5.13.1 Detecting and Enabling the Execute-Disable Capability 5-30 5.132 Execute-Disable Page protection 5.13.3 Reserved bit checking 5-31 5.134 Exception Handling........ 着鲁着,1,111.1能 ,5-32 CHAPTER 6 INTERRUPT AND EXCEPTION HANDLING 6.1 NTERRUPT AND EXCEPTION OVERVIEW 52 EXCEPTION AND INTERRUPT VECTORS 6,3 SOURCES OF INTERRUPT 6-2 6.3.1 External Interrupts 6-2 632 Maskable hardware Interrupts 6-3 633 Software-Generated Interrupts .6-4 6.4 SOURCES OF EXCEPTIONS 6-4 64.1 Program-Error Exceptions 着,日1着着着着11着B1 6-4 o L 3A V CONTENTS PAGE 64.2 Software-Generated Exceptions I000 ,,,,6-4 64.3 Machine-Check Exceptions..,...... 1鲁着 6-4 6.5 EXCEPTION CLASSIFICATIONS 6-5 66 PROGRAM OR TASK RESTART 6,7 NONMASKABLE INTERRUPT(NMI) 6-6 6.7.1 Handling Multiple NMis .6-6 68 ENABLING AND DISABLING INTERRUPTS 6-6 68.1 Masking maskable hardware Interrupts 6-6 68.2 Masking Instruction Breakpoints 683 Masking Exceptions and Interrupts when Switching Stacks.,.,.,.......... 69 PRIORITY AMONG SIMULTANEOUS EXCEPTIONS AND INTERRUPTS 6-8 6.10 INTERRUPT DESCRIPTOR TABLE (IDT) 6-9 6.11 IDT DESCRIPTORS 6-10 6.12 EXCEP TION AND INTERRUPT HANDLING 着1着着看11着1着 ,,6-11 6.12.1 Exception-or Interrupt-Handler Procedures 6-11 6.12.1 Protection of Exception-and Interrupt-Handler Procedures ,6-13 6.12.1.2 Flag Usage by Exception- or Interrupt-Handler procedure. ,,,6-14 6.12.2 Interrupt Tasks 6-14 6.3 ERROR CODE 6.14 EXCEP TION AND INTERRUPT HANDLING IN 64-BIT MOI 6-16 6.14.1 64-Bit Mode dt 6-16 6.14264-Bit№ ode stack e「ame,,, 着着1 ,6-17 6.143 IRET in IA-32e Mode 6-18 6. 14.4 Stack Switching in IA-32e Mode...,....,...,... 着1着 6-18 6. 14.5 Interrupt Stack Table 6-19 6.15 EXCEPTION AND INTERRUPT REFERENCE ,6-19 Interrupt 0-Divide Error Exception(#DE 1重11_着着 1着 6-20 Interrupt 1-Debug Exception ( DB 6-2 Interrupt 2-NMI Interrupt 鲁1重重 ,6-23 Interrupt 3-Breakpoint Exception #BP 6-24 Interrupt oVerflow Exception ( #OF) 11·盖 Interrupt 5-BOUND Range Exceeded Exception( #Br) 6-26 Interrupt 6-Invalid Opcode Exception(# UD) 6-27 Interrupt /-Device Not Available Exception (#NM) 6-28 Interrupt 8-Double Fault Exception (#DF) 6-29 Interrupt 9-Coprocessor Segment Overrun ,6-3 Interrupt 10-Invalid TSS Exception(#TS 着着 ∴6-32 Interrupt 11-Segment not Present ,,6-34 Interrupt 12-Stack Fault Exception (#ss ,6-36 Interrupt 13-General Protection Exception(#GP) 6-37 Interrupt 14-Page- Fault Exception( #PF) 6-40 Interrupt 16-X87 FPU Floating-Point Error(#MF) 着 6-43 Interrupt 17-Alignment Check Exception(#Ag) ,,6-45 Interrupt 18-Machine-Check Exception(#MC) 6-47 Interrupt 19-SIMD Floating-Point EXception(#XM) 6-48 Interrupt 20--Virtualization Exception ( #VE 6-50 Interrupts 32 to 255-User Defined Interrupts CHAPTER 7 TASK MANAGEMENT 7.1 TASK MANAGEMENT OVERVIEW 7-1 7.1.1 Task structure 7.1.2 Task state 7.1.3 Executing a Task.... TASK MANAGEMENT DATA STRUCTURES ,2 Task-State Segment (Tss 7.2.2 TSS Descriptor 7-5 7.2.3 TSS Descriptor in 64-bit mode 7-6 7.24 Task Registe 72.5 Task-Gate Descriptor.,.... 73 TASK SWITCHING .:.:::::.::.::: ,,,11着着着1 VI VoL, 3A CONTENTS PAGE 7.4 TASK LINKING 1重1鲁11着1着 74.1 Use of Busy Flag To Prevent Recursive Task Switching 1鲁着 7-13 74.2 Modifying Task Linkages ,,7-13 7.5 TASK ADDRESS SPACE 7-14 7,5.1 Mapping Tasks to the Linear and Physical Address spaces ,,,7-14 75.2 Task Logical Address space ∴..7-15 76 16-BIT TASK-STATE SEGMENT TSS 7-15 7,7 TASK MANAGEMENT IN 64-BIT MODE -16 CHAPTER 8 MULTIPLE-PROCESSOR MANAGEMENT LOCKED ATOMIC OPERATIONS8-1 8.1.1 Guaranteed Atomic operations 着1 着, 8-2 8.1.2 Bus Locking 8-3 3.1.2.1 Automatic Locking................... 8-3 8.1.22 Software Controlled Bus Locking 8-3 8.1.3 Handling Self- and Cross-Modifying Code 8-4 8.14 Effects of a loCK Operation on Internal Processor Caches 8-5 8.2 MEMORY ORDERING 8-5 8.2.1 Memory Ordering in the Intel Pentium and Intel486 Processors 8-6 82.2 Memory ordering in P6 and More recent processor Families 8-6 82.3 Examples Illustrating the Memary-Ordering Principles 8-7 823.1 Assumptions, Terminology and notation 8-8 8232 Neither Loads Nor stores Are reordered with like Operations 8-9 823.3 Stores are not reordered with earlier loads 8-9 82.34 oads May be reordered with earlier Stores to Different Locations 8-9 823.5 Intra-Processor Forwarding Is Allowed ..:....:::.. ,8-10 82.3.5 Stores Are Transitively visible....... ,8-10 82.3.7 Stores Are Seen in a Consistent Order by other Processors I1B I 8-11 82.38 Locked instructions have a total order 1着着11 8-1 8.239 oads and stores are not reordered with locked instructions 8-12 824 Fast-String Operation and out-of-Order Stores 8-12 8.24.1 Memory-Ordering Model for String Operations on Write-Back(WB)Memory 8-13 8.242 EXamples Illustrating Memory-ordering Principles for String Operations ··· 8-13 82.5 Strengthening or Weakening the Memory-Ordering Model 8-15 83 SERIALIZING INSTRUCTIONS 8.4 MULTIPLE-PROCESSOR (MP)INITIALIZATION ,8-18 84.1 BSP and ap processors 着1,重重 ,8-18 842 MP Initialization Protocol Requirements and restrictions 8-19 843 MP Initialization Protocol Algorithm for MP Systems 8-19 844 MP Initialization EXample. 8-20 844.1 Typical BSP Initialization Sequence 2 1、1111, 8442 Typical AP Initialization Sequence.,......... 84.5 dentifying logical processors in an mP system ,,8-23 8.5 INTEL HYPER-THREADING TECHNOLOGY AND INTEL MULTI-CORE TECHNOLOGY 8-24 86 DETECTING HARDWARE MULTI-THREADING SUPPORT AND TOPOLOGY ...8-24 86.1 Initializing Processors Suppor ting Hyper-Threading Technology 8-25 862 itializing Multi-Core Processors 863 Executing Multiple Threads on an Intel 64 or IA-32 Processor Supporting Hardware Multi-Threading ,...... 8-26 Handling Interrupts on an IA-32 Processor Supporting Hardware Multi-Threading 8-26 8.7 NTELR HYPER-THREADING TECHNOLOGY ARCHITECTURE ,,8-27 87.1 State of the Logical Processors ,8-28 87.2 APIC Functionality 8-29 87.3 Memory Type Range Registers MTRR ,8-29 374 Page Attribute Table(PAt) 着鲁,1,,4重 ∴8-29 8.7,5 Machine check architecture ∴8-29 8.7.6 Debug registers and EXtensions ..8-30 8.7.7 Performance monitoring counters .8-30 878 IA32 MISC ENABLE MSR ·,,11,1,里,1着着1 8-30 879 Memory ordering,..,.,.,.. ,8-30 8.7. 10 Serializing Instructions 8-30 87.1 Microcode update resources 8-30 87.12 8-31 8. 7. 13 Implementation-Specific Intel HT Technology facilities 8-3 oL, 3A ViI CONTENTS PAGE 87.13.1 Processor caches .:::.:::::::: 8-31 87.13.2 Processor Translation Lookaside Buffers (tlBs).......,.... ,8-31 87.13.3 Thermal monitor 8-32 87.134 External Signal Compatibility ,8-32 8. 8 MULTI-CORE ARCHITECTURE ,,8-32 88.1 Logical Processor Support 8-33 882 Memory Type Range Registers(MTRR 8-33 883 Performance Monitoring Counters.....,.... 8-33 884 lA32 MISC ENABLE MSR 8-33 88.5 Microcode Update resources ,8-33 8.9 PROGRAMMING CONSIDERATIONS FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS 8-34 89.1 Hierarchical Mapping of Shared Resources ∴,8-34 892 Hierarchical Mapping of CPUid Extended Topology Leat 8-36 893 Hierarchical id of Logical Processors in an MP System 8-38 893.1 Hierarchical id of logical Processors with x2APIC ID 着1 8-40 894 Algorithm for Three-Level Mappings of APIC_ID 着 8-40 895 Identifying Topological Relationships in a MP System ,8-45 8.10 MANAGEMENT OF IDLE AND BLOCKED CONDITIONS ..8-49 8.10.1 HLT Instruction ..8-49 8.102 PAUSE Iostruction 8-49 Detecting Support MONITOR/ MWAIT Instruction.……………… ,8-49 8104 MONITOR/MWAIT Instruction 8-50 8. 10.5 Monitor/Mwait Address range determination ,,,8-51 8.106 Required Operating system Support.,..,.....,. ,,8-51 8.10.6.1 Use the pause instruction in Spin-wait Loops 852 8.1062 Potential Usage of MoNITOR/MWAIT in CO ldle Loops. ,852 8.1063 Halt Idle Logical Processors 853 8.10.6.4 Potential Usage of MONITOR/MWAIT in C1 ldle Loops 8-54 8.106.5 Guidelines for Scheduling threads on logical processors sharing Execution Resources 8-54 8.1065 Eliminate EXecution-Based Timing Loops 8-55 8.106.7 Place Locks and Semaphores in Aligned, 1 28-Byte Blocks of Memory 8-55 8. 11 MP INITIALIZATION FOR P6 FAMILY PROCESSORS 8-55 8.11.1 Overview of the mp Initialization Process for p Family processors 8-55 8.11.2 MP Initialization Protocol algorithm 8-56 8.11.2.1 Error Detection and handling during the mp initialization protocol ,8-58 CHAPTER 9 PROCESSOR MANAGEMENT AND INITIALIZATION 9.1 INITIALIZATION OVERVIEW 9.1.1 Processor state After reset 9-2 9.1.2 Processor Built-In Self-Test BIST) 9.13 Model and stepping Information 1着1,11着1着着,面,重 9-5 9.1.4 First nstruction executed 9-5 92 X87 FPU INITIALIZATION 9-5 9.2.1 Configuring the x87 FPU Environment 9-6 922 Setting the Processor for x87 FPU Software Emulation 9-6 93 CACHE ENABLING 1着着11n着,11,1L, 94 MODEL-SPECIFIC REGISTERS MSRS)..... 9-7 9.5 MEMORY TYPE RANGE REGISTERS MTRRS 9-8 9.6 INITIALIZING SSE/SSEZ/SSE3/SSSB3 EXTENSIONS 9-8 SOFTWARE INITIALIZATION FOR REAL-ADDRESS MODE OPERATION 着着着 97.1 Real-Address mode idt 9-8 97.2 NMI Interrupt handling 9-9 98 SOFTWARE INITIALIZATION FOR PROTECTED-MODE OPERATION 99 8. Protected-Mode system Data Structures 982 Initializing protected-Mode Exceptions and Interrupts 9-10 98.3 Initializing Paging 9-10 984 Initializing Multitasking .9-10 98.5 Initializing IA-32e Mode 9-11 985 IA-32e Mode System Data Structures 98.5 IA-32e Mode Interrupts and Exceptions 9-12 9853 64-bit Mode and Compatibility Mode operation 9-12 985.4 Switching Out of IA-32e Mode Operation 9-12 9.9 MODE SWITCHING 重4, 9-13 VIlL VoL, 3A CONTENTS PAGE 99.1 Switching to Protected Mode........ .:::.:::::::::::...:.. 992 Switching back to Real-Address mode 9-14 9.10 INITIALIZATION AND MODE SWITCHING EXAMPLE 9-14 9.10.1 Assembler Usage.…,,, 9-16 9. 10.2 STARTUP. ASM Listing 9-15 9.10.3 MAINASM Source code 9.104 Supporting Files 9-25 9.11 MICROCODE UPDATE FACILITIES 9.11.1 Microcode Update..... ,,9-28 9. 11.2 Optional Extended Signature Table ,1着着重,·靠1着着,重,,·着1重 ,9-3 9.113 Processor ldentification 9-32 9.11. 4 Platform ldentification 9-32 9.115 Microcode Update checksum 9-33 9.116 Microcode update loader 9-34 9.11.6.1 Hard Resets in Update loading ............,.,.,..... ,9-35 91162 Update in a multiprocessor System ,9-35 9.11.63 Update in a System Supporting Intel Hyper-Threading Technology 9-35 9.11.64 Update in a System Supporting Dual-Core Technology 9-35 9.11.65 Update loader Enhancements 9-35 9. 11.7 Update Signature and verification 9-36 9.11.7,1 Determining the Signature ..,.... 9-36 9.11.7.2 Authenticating the Update 9-37 9. 11.8 Optional Processor Microcode Update Specifications 着着,1,1着1.,, 9-37 9.11.8.1 Responsibilities of the blos .9-38 9118.2 Responsibilities of the calling program 9-39 9.1183 Microcode Update functions 9-42 91184 INT 15H-based Interface 9-42 9118.5 Function ooh-presence test 9-42 9.11.85 Function 0TH-Wwrite Microcode Update Data 9-43 9.11.8.7 Function 02H-Microcode Update Control ..9-46 9.11.88 Function O3H-Read Microcode Update data ∴.,9-47 9.11.89 Return codes .9-48 CHAPTER 10 ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC 10.1 LOCAL AND V0 APIC OVERVIEW 10-1 10.2 SYSTEM BUS VS APIC BUS 10-4 10.3 THE INTEL82489DX EXTERNAL APIC, THE APIC, THE XAPIC, AND THE X2APIC .................................10-4 10.4 LOCAL APIC ,,10-4 104.1 The Local APIC Block Diagram ,,,10-4 104.2 Presence of the local apic 10-8 10.4.3 Enabling or Disabling the local apic ,10-8 1044 Local apic status and location 10-8 10.4.5 Relocating the Local APIC Registers 10-9 104.6 Local aPic id 10-9 104.7 Local apic state ..10-10 104.7.1 Local APiC State After Power-Up or Reset 11着 ,,10-10 104.72 Local apic state after It has been software disabled 重着1廉1,着1 10-11 104.7,3 Local APiC State After It Receives an INIT-Deassert ate). Local APlC State After an INIT Reset (wait-for-SIPI" State ,10-11 104.74 10-11 1048 Local APiC Version Register.,...,....... 1鲁着 10 10.5 HANDLING LOCAL INTERRUPTS 10-12 10,5.1 Local vector table 10-12 1052 Valid Interrupt Vectors............ 10-14 0.53 Error Handling 10-15 1054 APIC Timer 10-16 1054.1 TSC-Deadline mode .10-17 10.5.5 Local Interrupt Acceptance 10-18 10.6 SSUING INTERPROCESSOR INTERRUPTS 鲁1着 11着1,1,1 10-18 106.1 Interrupt Command Register ,,10-19 1062 Determining IPl Destination 10-23 1062.1 Physical Destination Mode 10-23 10622 Logical Destination Mode.,.....,..... ,10-23 10623 Broadcast/Self Delivery Mode.. ,,,10-25 vol.3Aⅸ CONTENTS PAGE 10.624 Lowest Priority Delivery Mode...............,..... ,10-25 10.6.3 IPl Delivery and Acceptance 重1·着鲁1着1重 1鲁着 10-26 10.7 SYSTEM AND APIC BUS ARBITRATION 10-26 10.8 HANDLING INTERRUPTS 10-26 108.1 Interrupt Handling with the pentium 4 and Intel Xeon Processor ,,10-27 10.8.2 Interrupt Handling with the pb Family and Pentium Processors 10-27 0.8.3 Interrupt, Task, and Processor Priority 10-28 108.3.1 Task and processor priorities 10-29 1084 Interrupt Acceptance for Fixed Interrupts 10-30 10.8.5 Signaling Interrupt Servicing Completion 着,1Dn1,重 10-31 1086 Task Priority in IA-32e Mode 10-31 1086.1 Interaction of task priorities between cr8 and apic 10-32 10.9 SPURIOUS INTERRUPT 10-32 10.10 APIC BUS MESSAGE PASSING MECHANISM AND PROTOCOL (P6 FAMILY, PENTIUM PROCESSORS).......... 10-33 10.10.1 Bus Message Formats.,,,,,,,,,,,,,,,,,,,,,,,,,, 10-34 0.11 MESSAGE SIGNALLED INTERRUPTS 着重 10-34 10.11 Message Address register Format ,,,,10-34 10.11. 2 Message Data Register Format 10-35 10.12 EXTENDED XAPIC (XZAPIO 10-36 10.12.1 Detecting and Enabling XZAPIC Mode 10-37 10.12.1.1 Instructions to Access APlC Registers 10-37 10.12.1. 2 X2APIC Register Address space 10-38 10.12.13 Reserved Bit checking.,.,.....,... ,10-40 10.12.2 X2APIC Register Availability..,....,........ 10-40 ..:::::::·::..::..:....:: 10.123 MSR Access in x2APIC Mode 10-40 10.12.4 VM-Exit Controls for MSRs and X2APIC Registers 1041 10.125 x2APIC State transitions 10-41 10.12.5.1 x2APIC States ,,,10-41 X2APIC After reset 10-42 x2APIC Transitions from x2APIC Mode 10-42 X2APIC Transitions from Disabled Mode .10-43 State Changes from aPLc Mode to x2APIC Mode 10-43 10.12.6 Routing of Device Interrupts in x2APIC Mode ,10-43 10.12.7 Initialization by System Software..........., 10-43 10.128 CPUID EXtensions And Topology Enumeration 1鲁着 ,10-43 10.128.1 Consistency of APIC iDs and CPUid 10-44 10.12.9 ICR Operation in X2APIC Mode 10-44 10.12.10 Determining IPl Destination in X2APIC Mode ,,10-45 10.12.10.1 Logical Destination Mode in x2APIC Mode 10-45 10.12.10.2 Deriving Logical X2APIC ID from the Local X2APIC ID .10-46 10.12.11 SELF IPI Register.. .10-47 10.13 APIC BUS MESSAGE FORMATS 10-47 10.13. 1 Bus Message Formats. 111L1 10-47 10.13.2 EOl Message ,10-47 10.132.1 Short Message 10-48 10.13.2.2 Non-focused Lowest priority Message 10-49 10.13.2.3 APIC Bus Status Cycles 10-50 CHAPTER 11 MEMORY CACHE CONTROL 11.1 NTERNAL CACHES, TLBS, AND BUFFERS 11.2 CACHING TERMINOLOGY 11-5 11.3 METHODS OF CACHING AVAILABLE 11-6 11.3.1 Buffering of Write Combining Memory Locations 1132 Choosing a Memory Type 11-8 113.3 ode fetches in Uncacheable memory ...,.. ,,11-9 11.4 CACHE CONTROL PROTOCOI 11-9 11,5 CACHE CONTROL n着4,重 11-10 115.1 Cache Control Registers and Bits ,,11-10 115.2 Precedence of cache controls 11-13 Selecting Memory Types for Pentium Pro and Pentium ll Processors ,,11-14 1.5.2.2 Selecting Memory Types for Pentium ll and More recent processor Families ...... ......................11-15 115.23 Writing Values Across Pages with Different Memory Types 11-16 X VoL. 3A

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