armv8m_architecture_memory_protection_unit_100699_

文件名称: armv8m_architecture_memory_protection_unit_100699_0100_00_en.pdf

所属分类: 其它

开发工具:

文件大小: 520kb

下载次数: 0

上传时间: 2019-10-12

提供者: zyn13*****

下载 (520kb)

不能下载？报告错误

详细说明：The Memory Protection Unit (MPU) is a programmable unit that allows privileged software to define memory access permissions for up to 16 separate memory regions. This chapter provides an overview of the MPU programmers' model and summarizes its key features.Memory Protection Unit(MPU) Product status The information in this document is Final, that is for a developed product. Web Address http://www.arm.com ARM100699010000en Copyright C 2016 ARM. All rights reserved Contents Memory Protection Unit ( MPU) Preface About this book Feedback Chapter 1 Introduction 1.1 About the mPu 1-13 1.2 Key features of the MPU 1-14 1.3 MPU programmers'model changes for the ARM v8-M architecture 1-15 Chapter 2 Memory type definitions 2.1 Memory type definitions in the ARM v8-M architecture 2-17 2.2 Memory system and memory partitioning 2-21 Chapter 3 Memory configuration 3.1 MPU registers 3-23 3.2 Attribute indirection 3-25 Chapter 4 Register definitions 4.1 MPU TYPE 4-27 4.2 MPU CTRL 4-28 4.3 MPU RNR 4-30 4.4 MPU RBAR 4-31 4.5 MPU RLAR 4-33 4.6 MPU RBAR A1/2/3 and MPU RLAR A1/2/3 4-34 ARM100699010000en Copyright C 2016 ARM. All rights reserved 4.7 MPU MAIRO MPU MAIR1 4-35 4.8 Configuring an MPU region 4-36 Chapter 5 CMSIS MPU support 5.1 CMS/S-CORE 5-39 ARM100699010000en Copyright C 2016 ARM. All rights reserved ∧on- Confidentia List of Figures Memory Protection Unit ( MPU) Figure 1 Key to timing diagram conventions 10 Figure 1-1 MPU memory regions aB4aa“ 1-15 Figure 2-1 Shareability groups 2-19 Figure 3-1 Attribute indirection 3-25 Figure 4-1 MPU TYPE bit assignments.….… 4-27 Figure 4-2 MPU CTRL bit assignments 4-28 Figure 4-3 MPU RNR bit assignments 4-30 Figure 4-4 MPU RBAR bit assignments 4-31 Figure 4-5 MPU RLAR bit assignments 4-33 Figure 4-6 MPU MAIRO, MPU MAIR1 bit assignments 4-35 Figure 4-7 Configuring an MPU region 4-37 ARM100699010000en Copyright C 2016 ARM. All rights reserved List of tables Memory Protection Unit ( MPU) Table 2-1 Cache attributes 2-18 Table 3-1 MPU registers .3-23 Table 4-1 MPU TYPE bit assignments 4-27 Table 4-2 MPU CTRL bit assignments 4-28 Table 4-3 MPU RNR bit assignments.... 4-30 Table 4-4 MPU RBAR bit assignments .4-31 Table 4-5 MPU RLAR bit assignments 4-33 Table 5-1 Standardized names for MPU registers............ 5-39 ARM100699010000en Copyright C 2016 ARM. All rights reserved Preface This preface introduces the Memory Protection Unit (MPU) It contains the following About this book on page 9. Feedback on page 11 ARM100699010000en Copyright C 2016 ARM. All rights reserved 8 ∧on- Confidentia Preface About this book About this book Product revision status The rmpn identifier indicates the revision status of the product described in this book, for example, rlp2, rm Identifies the major revision of the product, for example, rl pn Identifies the minor revision or modification status of the product, for example, p2 Intended audience Using this book This book is organized into the following chapters Chapter 1 Introduction The Memory Protection Unit (MPu) is a programmable unit that allows privileged software to define memory access permissions for up to 16 separate memory regions. This chapter provides an overview of the mpu programmers' model and summarizes its key features Chapter 2 Memory type definitions In the ARMv8-M architecture, memory types are divided into Normal Memory and Device Memory. If the arMv8-M architecture with Security Extension is implemented, the memory space is partitioned into Secure and Non-secure memory regions Chapter 3 Memory configuration The MPU is configured by a series of memory mapped registers in the System Control space (SCS). This chapter lists the MPU registers, and describes the attribute indirect mechanism that allows multiple mPu regions to share a set of memory attributes Chapter 4 Register definitions This chapter shows the bit assignments for cach of the MPU registers Chapter 5 CMSIS MPU support ARMv8-M processors provide software support with an initiative called the Cortex Microcontroller Software Interface Standard(CMSIS). This chapter lists the standardized names for MPU registers, and provides configuration settings to initialize CMSIS MPU. Glossary The ARM Glossary is a list of terms used in ARM documentation, together with definitions for those terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning See the aRM Glossary for more information Typographic conventions Introduces special terminology, denotes cross-references, and citations Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive lists, where appropriale monospace Denotes text that you can enter at the keyboard, such as commands, file and program names and source code monospace Denotes a permitted abbreviation for a command or option You can enter the underlined text nstead of the full command or option name ARM100699010000en Copyright C 2016 ARM. All rights reserved Preface About this book monospace italic Denotes arguments to monospace text where the argument is to be replaced by a specific value monospace bold Denotes language keywords when used outside example code. Encloses replaceable terms for assembler syntax where they appear in code or code fragments For example MRC p15, 0, ,, , SMALL CAPITA Used in body text for a few terms that have specific technical meanings, that are defined in the aRM glossary For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and UNPREDICTABLE Timing diagrams The following figure explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams Shaded bus and signal areas are undefined so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation HIGH to LoW: Transient V HIGH/LOW to HIGH Bus stable Bus to high impedance changeR High impedance to stable bus X Figure 1 Key to timing diagram conventions Signals The signal conventions are Signal level The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW asserted means HIGH for active-HIGH signals LOW for active-LOW signals Lowercase n At the start or end of a signal name denotes an active-LOW signal ARM100699010000en Copyright C 2016 ARM. All rights reserved

(系统自动生成,下载前可以参看下载内容)