Luminary Micro Stellaris系列LM3S812微控制器数据手册(周立功翻译).p

文件名称: Luminary Micro Stellaris系列LM3S812微控制器数据手册(周立功翻译).pdf

所属分类: 其它

开发工具:

文件大小: 4mb

下载次数: 0

上传时间: 2019-10-12

提供者: weixin_********

下载 (4mb)

不能下载？报告错误

详细说明：Luminary Micro Stellaris系列LM3S812微控制器数据手册(周立功翻译)pdf,Luminary Micro Stellaris系列LM3S812微控制器数据手册(周立功翻译)LM3S812 Microcontroller Table of Contents About this document,…… 17 Audience 7 About this manual 17 Related documents 画1 17 Documentation conventions 17 Architectural overview ■■重■m 19 Product features 19 1.2 Target Applications 24 1.3 High-Level Block Diagram 24 Functional overview 25 1.4.1 ARM CortexTM-M3 iaiiaiiiiia 26 1.4.2 Motor Control Peripherals 26 1.4.3 Analog Peripherals 27 1.4.4 Serial Communications Peripherals 28 1.4.5 System Peripherals 翻国E 29 1.4.6 Memory Peripherals 29 1.4.7 Additional features 30 1.4.8 Hardware Details 31 1.4.9 System Block Diagram 32 ARM Cortex-M3 Processor 2.1 Block Diagram 34 2.2 Functional Description…… 34 2.2. 1 Serial Wire and JTAG Debug 34 2.2.2 Embedded Trace Macrocell (ETM) 35 2.2.3 Trace Port Interface Unit (TPIU) 35 2.2.4 ROM Table 35 2.2.5 Memory Protection Unit(MPU) ∴35 2.2.6 Nested Vectored Interrupt Controller(NVIC) ∴35 Memory Map D■■■口■口圆D■■■口重■■ 39 Interrupts∴ 41 JTAG Interface m.m......mmo.. 43 5.1 Block Diagram ... 44 Functional Description 44 5.2.1 JTAG Interface Pins 45 5.2.2 JTAG TAP Controller 46 5. 2. 3 Shift Registers .47 5.2.4 Operational considerations 47 5.3 Initialization and configuration 48 5. 4 Register Descriptions 49 5.4.1 Instruction Register(IR) 49 5.4.2 Data Registers System Control 53 Functional Description 53 6.1.1 Device Identification ·.· 53 November 29.2007 3 Preliminary Table of contents 6.1.2 Reset Control 53 6.1.3 Power Control 56 6.1.4 Clock Control 56 6.1.5 System Contro 翻量“ 59 6.2 Initialization and Configuration E面1面E 59 6.3 Register Map… .60 6.4 Register Descriptions∴……… 61 Internal Memory 112 7.1 Block Diagram ∴112 7.2 Functional Description 112 7. 2. 1 SRAM Memory 112 7.22 Flash Memory………… .113 3 Flash Memory Initialization and Configuration 115 7.3.1 Changing flash protection Bits…… 115 7.3.2 Flash Programming .116 7.4 Register Map .116 7.5 Flash Register Descriptions(Flash Control Offset) 117 7.6 Flash Register Descriptions(System Control Offset 124 8 Genera|- Purpose Input/Outputs(GP|os)…,…,… ■重国口日■口■■■ 128 8.1 Block Diagram… dabiaia0di b 129 8.2 Functional Description 129 8.2.1 Data Control 130 8.2.2 Interrupt Control 131 8.2.3 mode control 132 8.2.4 Pad Control 132 8.2.5 Identification 1132 8.3 Initialization and configuration 132 8.4 Register Map 133 8.5 Register D 135 Genera|- Purpose Timers…,,,,,,…,…,"…,,…,…,…,…167 9.1 Block dia 167 9.2 Functional Description 168 9.2.1 GPTM Reset conditions 168 9. 2.2 32-Bit Timer Operating Modes 169 9.2.3 16-Bit Timer Operating Modes 170 9.3 Initialization and configuration 174 9.3.1 32-Bit One-Shot/Periodic Timer mode 174 9.3.2 32-Bit Real-Time Clock(RTC)Mode 175 9. 3.3 16-Bit One-Shot/Periodic timer mode 面面 ..175 93416- Bit Input Edge Count Mode…… .176 9.3.5 16-Bit Input Edge Timing Mode 176 9.3.616- Bit pwm mode∴ 177 9.4 Register Map 177 9. Register Descriptions 178 10 Watchdog timer… 203 10.1 Block Diagram 203 10.2 Functional Description 203 November 29 2007 Preliminary LM3S812 Microcontroller 10.3 Initialization and Configuration 204 10.4 Register Map 204 10.5 Register Descriptions…… 205 11 Analog-to-Digital Converter(ADC) 226 11. 1 Block Diagram 227 11.2 Functional Description 227 11.2.1 Sample Sequencers .... 227 11.2.2 Module control 228 11.2.3 Hardware Sample Averaging Circuit .229 11.24 Analog- to-Digital Converter….… ..229 11.2.5 Test Modes .229 11.26 nternal Temperature Sens。r… 229 11.3 nitialization and Configuration…… 230 11.3.1 Module Initialization 230 11.3.2 Sample Sequencer Configuration ..230 11.4 Register Map 231 11.5 Register Descriptions 232 Universal Asynchronous Receivers/Transmitters (UARTs) 259 12.1Blocκ Diagram… 260 12.2 Functional Description 260 12.2.1 Transmit/Receive Logic ..;..::::: 260 12.2.2 Baud-Rate Generation 261 12.2.3 Data transmission 262 12.2.4 FIFO Operation 262 12.2.5 Interrupts ..... 262 12.2.6 Loopback Operation 263 12.3 Initialization and Configuration 263 12.4 Register Ma 264 12.5 Register D 265 13 Synchronous Serial Interface(ssi) 297 13. 1 Block Dia 297 13.2 Functional Description…..… 画1 297 13.2.1 Bit Rate generation 298 13. 2. 2 FIFO Operatic 298 13.2.3 Interrupts 298 13.2.4 frame Formats 1面 .299 13.3 Initialization and Configuration…… 306 13.4 Register Map 307 13.5 Register Descriptions 1, 308 14 Inter-Integrated Circuit (IC 14.1 Block Diagram. 14.2 Functional description 334 14.2.112C Bus Functional Overview 335 14.2.2 Available speed Modes 337 14.2.3 Interrupts 338 14.2. 4 Loopback Operation 338 14.2.5 Command Sequence Flow Charts 339 November 29.2007 Preliminary Table of contents 14.3 Initialization and configuration 345 14.4 |2C Register Map 346 14.5 Register Descriptions(I-C Master) 347 14.6 Register Descriptions(12C Slave) 360 Analog comparator∴ 369 15.1 Block Diagram 369 15.2 Functional Description 369 15.2.1 Internal Reference Programming 370 15.3 Initialization and configuration 371 154 Register Map… 372 15.5 Register Descriptions .372 16 Pulse width Modulator(PWM)…,…,…,…,,…,…,…,…,…,,…,…,,…………380 16.1 Block Diagram 380 16.2 Functional Description 380 16.21 PWM Timer 380 16.2.2 PWM Comparators ∴381 16.2.3 PWM Signal Generator .382 16.2.4 Dead-Band generator 383 16.2.5 Interrupt/ADC-Trigger Selector 383 16.2.6 Synchronization Methods 383 16.2.7 Fault conditions 384 16.2.8 Output Control Block 384 16.3 Initialization and configuration 画1 1, 384 16.4 Register Map 385 16.5 Register Descriptions 386 17 Pin Diagram me.mm. ■■口■■■■■m■■■■■■■■1圆■口■重,■■口■口口量■D■■量■■■口■■m■■■D■■m 415 18 Signal Tables 416 perating Characteristics 423 20 Electrical Characteristics 20.1 DC Characteristics 424 20.1.1 Maximum Ratings 424 20.1.2 Recommended DC Operating Conditions 424 20.1.3 On-Chip Low Drop-Out( LDO) Regulator Characteristics .“: 1 425 20.1. 4 Power specifications 425 20.1.5 Flash Memory Characteristics 426 20.2 AC Characteristics 426 20.21 Load conditions 426 20.2.2 Clocks 426 20.2.3 Analog-to-Digital Converter 427 20.2.4 Analog Comparator 427 20.2.512C .428 20.2.6 Synchronous Serial Interface(SSI) 428 20.2.7 JTAG and Boundary scan 430 20.2.8 General-Purpose /o 431 20.2.9 Reset 432 November 29 2007 Preliminary LM3S812 Microcontroller 21 Package Information,,,.,.,.,.,.,,…,… ■口口重■口a■a重 435 A Serial flash A.1 Serial flash loader E面 437 A2 Interfaces 437 A.2.1 UART .437 A.2.2 SS 437 A3 Packet Handling 438 A.3.1 Packet format∴ 438 A.3.2 Sending packets 438 A 3.3 Receiving packets 438 A.4 Commands 439 A.4.1 COMMAND PING (0X20) 439 A.4.2 COMMAND_ GET STATUS(OX23 439 A.4.3 COMMAND DOWNLOAD(0X21 1画画 439 A.4.4 COMMAND SEND DATA(0X24) 440 A 4.5 COMMAND RUN (0X22) 440 A 4.6 COMMAND_ RESET(0X25) 440 Register quick Reference. c Ordering and Contact Information mmmneeamem 456 C 1 Ordering Information 456 C2 Kits 456 C3 Company Information 456 C 4 Support Information 457 November 29.2007 Preliminary Table of contents List of Figures Figure 1-1. Stellaris 800 Series High-Level Block Diagram 25 Figure 1-2. LM3S812 Controller System-Level Block Diagram .32 Figure 2-1. CPU Block Diagram 34 Figure 2-2. TPu block diagram .35 Figure 5-1. JTAG Module Block Diagram 44 Figure 5-2. Test Access Port State Machine 47 Figure 5-3. IDCODE Register Format Figure 5-4. BYPASS Register Format ........ 51 Figure 5-5. Boundary Scan Register Format 52 Figure 6-1. External Circuitry to Extend Reset 54 Figure 6-2. Main Clock Tree 57 Figure 7-1. Flash Block Diagram 112 Figure 8-1. GPIO Module Block Diagram .129 Figure 8-2. GPlO Port Block Diagram 130 Figure 8-3. GPIODATA Write Example 131 Figure 8-4. GPIO DATA Read Example 131 Figure 9-1. GPTM Module Block Diagram .168 Figure9-2.16- Bit Input Edge Count Mode Example……………………,172 Figure 9-3. 16-Bit Input Edge Time Mode Example 173 Figure 9-4. 16-Bit PWM Mode Example 174 Figure 10-1. WDT Module block Diagram 203 Figure 11-1. ADC Module Block Diagram .227 Figure11-2. nternal Temperature Sensor Characteristic……… 230 Figure 12-1. UART Module Block Diagram 260 Figure 12-2. UART Character Frame ..261 Figure 13-1. Ssl Module block Diagram 297 Figure 13-2. TI Synchronous Serial Frame Format (Single Transfer) 299 Figure133. TI Synchronous Serial Frame Format( Continuous transfer)……………300 Figure 13-4. Freescale SPI Format(Single Transfer )with SPo=0 and SPH=O .301 Figure13-5. Freescale sPl format( Continuous transfer) with sPo=0 and sPh=0………………….301 Figure 13-6. Freescale SPI Frame Format with SPo=0 and SPH=1 302 igure 13-7. Freescale SPI Frame Format(Single Transfer)with SPo=1 and SPH=0...... 303 Figure 13-8. Freescale SPI Frame Format (Continuous transfer) with SPo=1 and SPH=O 303 Figure 13-9. Freescale SPI Frame Format with SPo=1 and SPH=1 304 Figure 13-10. MICROWIRE Frame Format(Single Frame) 305 Figure 13-11. MICROWIRE Frame Format(Continuous Transfer) 306 Figure13-12.M| CROWIRE Frame Format, SSIFss Input Setup and Hold Requirements…………306 Figure 14-1. IC Block Diagram 334 Figure 14-2. IC Bus Configuration 335 Figure 14-3. START and stoP Conditions 335 Figure 14-4. Complete Data Transfer with a 7-Bit Address 336 Figure 14-5. R/s Bit in First Byte 336 Figure 14-6. Data Validity During Bit Transfer on the [2C Bus 336 Figure 14-7. Master Single SEND 339 Figure 14-8. Master Single RECEIVE 340 November 29 2007 Preliminary LM3S812 Microcontroller Figure 14-9. Master Burst SEND 341 Figure 14-10. Master Burst RECEIVE 342 Figure 14-11. Master Burst RECEIVE after Burst SEND 343 Figure 14-12. Master Burst SEND after Burst RECEIVE ..344 Figure 14-13. Slave Command Sequence 345 Figure 15-1. Analog Comparator Module Block Diagram 369 Figure 15-2. Structure of Comparator Unit .370 Figure 15-3. Comparator Internal Reference Structure 371 Figure16-1. PWM Module Block Diagram……… 380 Figure 16-2. PWM Count-Down Mode 381 Figure16-3. PWM Count-Up/ Down mode...…… 国国画 382 Figure 16-4. PWM Generation EXample In Count-Up/Down Mode 382 Figure16-5. PWM Dead- Band generator……… 383 Figure17-1. Pin Connection Diagram…,,…… 415 Figure 20-1. Load Conditions 426 Figure 20-2. 1-C Timing 428 Figure 20-3. SSl Timing for TI Frame Format(FRF=01), Single Transfer Timing Measurement . .............429 Figure 20-4. SSI Timing for MICROWIRE Frame Format(FRF=10), Single Transfer 2429 Figure 20-5. SSI Timing for SPI Frame Format(FRF=00), with SPH=1 430 Figure 20-6. JTAG Test Clock Input Timing 431 Figure 20-7. JTAG Test Access Port(TAP)Timing 431 Figure 20-8. JTAG TRST Timing 431 Figure 20-9. External Reset Timing(RST) ..432 Figure20-10. Power- On Reset Timing.…… 433 Figure 20-11. Brown-Out Reset Timing 433 Figure 20-12. Software Reset Timing 433 Figure 20-13. Watchdog Reset Timing 434 Figure 20-14. LDO Reset Timing .434 Figure 21-1. 48-Pin LQFP Package I.... 435 November 29.2007 Preliminary Table of contents List of Tables Table 1 Documentation Conventions 17 Tabe3-1. Memory Map…… 39 Table 4-1 Exception Types…… 41 Table 4-2 errupts 42 Table 5-1 JTAG Port pins reset state 45 Table 5-2. JTAG Instruction Register Commands 49 Table6-1. System Control Register Map…… 60 Table 6-2. pll mode control 75 Table 7-1 Flash Protection Policy Combinations 114 Tabe7-2. Flash Register Map…… 117 Table 8-1. GPlO Pad Configuration Examples 132 Table 8-2. GPIO Interrupt Configuration EXample 133 Table 8-3. GPIO Register Map 134 Table 9-1 Available ccP pins ∴168 Table 9-2 16-Bit Timer With Prescaler Configurations 171 Table 9-3. Timers Register Map 177 Table 10-1. Watchdog Timer Register Map 204 Table 11-1. Samples and FIFO Depth of Sequencers 227 Table 11-2. ADC Register Map 面1面面 231 Tabe12-1. UART Register Map…… 264 Table 13-1. SSI Register Map ,307 Table 14-1. Examples of IC Master Timer Period versus Speed Mode 337 Table 14-2. Inter-Integrated Circuit(I-C) Interface Register Map 346 Tabe143. Write Field Decoding for I2CMCS[3:0] Field( Sheet1of3)……………………,351 Table 15-1. Comparator 0 Operating Modes 370 Table 15-2 ernal Reference Voltage and ACREFCTL Field Values 371 Table 15-3. Analog Comparators Register Map 372 Tabe16-1. PWM Register Map………… 1国面B面面面1面 385 Table 18-1. Signals by Pin Number 416 Table 18-2. Signals by Signal Name 418 Table 18-3. Signals by Function, Except for GPIO 420 Table 18-4. GPIO Pins and alternate functions .“: 421 Table 19-1. Temperature Characteristics 423 Table 19-2. Thermal Characteristics 423 Table 20-1. Maximum Ratings 424 Table 20-2. Recommended DC Operating Conditions 424 Table 20-3. LDO Regulator Characteristics 425 Table 20-4. Detailed Power Specifications 425 Table 20-5. Flash Memory Characteristics 426 Table 20-6. Phase Locked Loop(PLL) Characteristics 426 Table 20-7. Clock Characteristics 426 Table20-8. ADC Characteristⅰcs∴ .427 Table 20-9. Analog comparator characteristics 427 Table 20-10. Analog Comparator Voltage Reference Characteristics .427 Table 20-11. 2C Characteristics 428 Table 20-12. Ss Characteristics 428 November 29 2007 Preliminary

(系统自动生成,下载前可以参看下载内容)