JEDEC JESD79-4B-2017 DDR4 SDRAM.pdfJEDEC STANDARD

文件名称: JEDEC JESD79-4B-2017 DDR4 SDRAM.pdf

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详细说明：JEDEC STANDARD DDR4 SDRAM JESD79-4B (Revision of JESD79-4A, November 2013) JUNE 2017 JEDEC Standard no, 79-4B DDRA SDRAM STANDARD Contents DDR4 SDRAM Package Pinout and Addressing 2.1 DDR4 SDRAM Row for x4 x8 and x16 着面 2.2 DDR4 SDRAM Ball Pitch 2222 2. 3 DDR4 SDRAM Columns for x4 x8 and x16 2. 4 DDR4 SDRAM X4/8 Ballout using MO-207 2.5DDR4 SDRAMⅩ16 Ballout using MO-207.…… aa11面面 3 2.6 DDR4 SDRAM X32 Ballout using MO-XXX 2.7 Pinout descripti 6 2.8DDR4 SDRAM Addressing……… 2. 9 DDP Single Rank(sr)x16 from two x8 9 3 Functional Description ... 3. 1 Simplified State Diagram 3.2 Basic Functionality .12 3. 3 RESEt and initialization procedure 3.3.1 Power-up Initialization Sequence ........ 12 3.3.2 VDD Slew rate at Power-up Initialization Sequence 13 3.3.3 Reset initialization with stable power 14 3. 4 Register Definition 3.4.1 Programming the mode registers 1-4 3.5 Mode Register 4 DDR4 SDRAM Command Description and operation .............. 4.1 Command truth table 28 4.2 CKE Truth Table aaa“ 4.3 Burst Length, Type and order…… 4.3.1 bl8 Burst order with crc enabled 4.4 DLL-off Mode DLL on/off Switching procedure 31 4.4.1 DLL on/off switching procedure 4.4.2DLL“on" to dll“ off procedure 31 4. DLL off to dll"on " procedure 32 4.5 DLL-off mode .33 4.6 Input Clock Frequency Change 34 4.7 Write Leveling..… 35 4. 7. 1 DRAM setting for write leveling dram termination function in that mode 4.7.2 Procedure Description 36 4.7.3 Write Leveling mode exit 4.8 Temperature controlled refresh modes 38 4.8.1 Normal temperature mode(0 C = TCASE=< 85C) 38 4.8.2 Extended temperature mode(0C=< TCASE=< 95C 4. 9 Fine Granularity Refresh Mode... 39 4. 9. 1 Mode register and command Truth table 39 4.9.2 tREF and tRFC parameters 4.9.3 Changing Refresh Rate 40 4.9. 4 Usage with Temperature Controlled Refresh mode 41 4.9.5 Self Refresh entry and exit 41 4.10 Multi Purpose Register………… 41 4.10.1 DQ Training with MPR 41 4.10.2 mR3 definition 41 4.10.3 MPR Reads 42 4.10 4 MPR Writes 4.10.5 MPR Read data formal…… 47 4.11 Data Mask(DM), Data Bus Inversion(DBI)and TDQS 52 JEDEC Standard No. 79-4B 4.12 ZQ Calibration Commands .54 4.12. 1 zQ Calibration Description 111 111a面c 54 4.13 DQ Vref Training 55 4.13.1 Example scripts for VrefdQ calibration mode 58 4. 14 Per DRAM Addressability 61 4. 15 CAL Mode(cs_n to Command Address Latency) 61 4.15.1 CAL Mode Description 63 4.15.2 Self Refresh Entry, Exit Timing with CAL .“ 66 4. 15. 3 Power Down Entry, Exit Timing with CAL 66 4. CRC 68 4.16. 1 CRC Polynomial and logic equation ..68 4. 16.2 CRC data bit mapping for x8 devices 69 4.16.3 CRC data bit mapping for x4 devices 69 4. 16.4 CRC data bit mapping for x16 devices 69 4.165 Write crc for x4 x8 and x16 devices 4. 16.6 CRC Error Handling 70 4.16.7 CRC Frame format with bc4 71 4.16.8 Simultaneous DM and Crc Functionality 4.16.9 Simultaneous mPr Write, Per DRAM Addressability and CRC Functionality….……… 73 4.17 Command Address Parity(Ca Parity) 74 4.17.1 CA Parity Error Log readout 80 4.18 Control gear-down mode 81 4.19 DDR4 Key Core Timing 83 4.20 Programmable Preamble 86 420.1 Write Preamble 8 420.2 Read Preamble ..88 4.20.3 Read Preamble training 88 4.21 Postamble 89 421.1 Read Postamble 89 4.212 Write Postamble 89 4.22 ACTIVATE Command 89 4.23 Precharge Command 89 4.24 Read Operation a.“aaa 90 4.24. 1 READ Timing Definitions 4.24.1.1 READ Timing Clock to Data Strobe relationship 4.24.1.2 READ Timing Data Strobe to Data relationship 4.24.1.3 tLZ(DQS), Lz(DQ), tHz(DQS), tHz(DQ) Calculation :: 94 4.24.1 4 tRPRE Calculation 4.24,1.5 tRPST Calculation 97 4.24.2 READ Burst Operation 98 4.24.3 Burst Read Operation followed by a precharge……… .109 4. 24.4 Burst Read Operation with Read DBI(Data Bus Inversion) 111 4.24.5 Burst Read Operation with Command/Address parity 112 4. 24.6 Read to write with Write crc 113 4.24.7 Read to Read with Cs to ca latency 4.25 Write Operation 115 4.25. 1 Write T iming parameters 115 4.25.2 Write data mask 116 4 25.3 tWPRE Calculation 117 4.25. 4 tWPST Calculation 118 4.25.5 Write Burst Operation .119 425. 6 Read and write command interval 134 4. 25.7 Write Timing Violations 135 4.25.7. 1 Motivation 135 4.25.7.2 Data Setup and hold offset violations 135 4.25.7.3 Strobe and strobe to Clock Timing violations 135 4.26 Refresh command 135 4.27 Self refresh Operation 137 427. 1 Low Power Auto self refresh 138 JEDEC Standard no, 79-4B 4.27.2 Self Refresh EXit with No Operation command 139 4.28 Power down mode 140 4. 28.1 Power-Down Entry and exit 140 428.2 Power-Down clarifications 144 4. 28.3 Power Down Entry and Exit timing during Command/Address Parity Mode is Enable 145 4. 29 Maximum Power Saving Mode 146 4. 29. 1 Maximum power saving mode 146 4.29.2 Mode entry 146 4.29.3 CKE transition during the mode 147 4.29. 4 Mode exit 147 4.29.5 Timing parameter bin of maximum Power Saving Mode for DDR4-1600/ 1866/2133/2400/2666/3200 148 4.30 Connectivity Test Mode 148 430.1Introduction 148 4.30.2 Pin Mapping 148 4.30.3 Logic Equations…… 149 4.30. 3 1 Min Term Equations 149 4.30.3.2 Output equations for x16 devices 150 4.30.3. 3 Output equations for x8 devices aa“a“““““““:: .150 40.. 4 Output equations for x4 devices 150 4.30. 4 Input level and Timing Requirement 151 4.30.5 Connectivity Test( CT )Mode Input Levels 152 4.30.5.1 Input Levels for RESETn 153 4.30.5.2 Input Levels for ALERT_n 153 4.31 CLK to Read DQs timing parameters 154 4.32 Post Package Repair(hPPR) 156 4.32. 1 Hard Fail Row Address Repair(Wra case) 156 4.32.2 Hard Fail Row Address Repair(WR Case) 157 4.32.3 Hard Fail row Address repair mr bits and timing diagram .157 4.32. 4 Programming hPPR& sPPR support in MPRo page2 158 4.32. 5 Required T iming Parameters 159 4.33 Soft Post Package Repair(sPPR) ∴4159 4.33.1 Soft Repair of a Fail Row Address 160 5 On-Die Termination 161 5. 1 ODT Mode register and odt state Table 161 5.2 Synchronous ODT Mode 163 5.2. 1 OdT Latency and posted odt 164 5.2.2 Timing Parameters 164 5.2.3 OdT during Reads 166 5.3 Dynamic OdT 167 5. 3. 1 Functional Description 167 5.3.2 ODT Timing Diagrams 168 5. 4 Asynchronous ODT mode 169 5.5 odt buffer disabled mode for power down “L11 170 5.6 ODT Timing Definitions 171 5.6. 1 Test Load for ODT Timings ... 171 5.6.2 ODT Timing Definitions 174 6 Absolute Maximum Ratings 174 7 AC and DC Operating Conditions…………… 174 8 AC and DC Input Measurement Levels 174 8.1 AC and dC Logic input levels for single-ended signals 174 8.2 AC and dC Input Measurement Levels: VREF Tolerances 175 8.3 AC and DC Logic Input Levels for Differential Signals 8.3.1 Differential signal definition 832 Differential swing requirements for clock(CKt-CKc)………… 8.3.3 Single-ended requirements for differential signals 177 8.3.4 Address, Command and Control Overshoot and Undershoot specifications 178 8.3.5 Clock Overshoot and Undershoot Specifications 179 8.3.6 Data, Strobe and mask Overshoot and Undershoot Specifications 180 8.4 Slew Rate Definitions 181 JEDEC Standard no, 79-4B 8.4.1 Slew Rate Definitions for Differential Input Signals( CK) ..181 8.4.2 Slew Rate Definition for Single-ended Input Signals( CMD/ADD) 182 8.5 Differential Input Cross Point Voltage .182 8.6 CMOS rail to rail Input Levels ““ 183 6. 1 CMOS rail to rail Input Levels for RESEt n 183 8.7 AC and dC Logic Input Levels for dQs signals 184 8.7.1 Differential signal definition .... .184 8.7.2 Differential swing requirements for dQs (DQs t-DQsC 184 8.7.3 Peak voltage calculation method 185 8.7.4 Differential Input Cross Point Voltage 186 8.7.5 Differential Input Slew Rate Definition 187 9 AC and dc output measurement levels …188 9.1 Output Driver DC Electrical Characteristics 188 9.1.1 Alert n output Drive Characteristic 190 9.1.2 Output Driver Characteristic of Connectivity Test( CT )Mode 191 9.2 Single-ended AC DC Output Levels... 191 9.3 Differential AC DC Output Levels 192 4 Single-ended Output Slew Rate 192 9.5 Differential Output Slew Rate 193 9.6 Single-ended AC dC Output Levels of Connectivity Test Mode 194 9.7 Test Load for Connectivity Test Mode Timing 194 10 Speed Bin…,,,.,...,,.,...,,.,,…… 195 10. 1 Speed Bin Table Note 203 11| DD and iddQ specification Parameters and Test conditions.………,……204 11.1 DD IPP and IDDQ Measurement Conditions 204 11.2 IDD Specifications 219 12 Input/Output Capacitance…… 221 13 Electrical Characteristics and Ac Timing………………,…,……,,…,………,……………………………224 13. 1 Reference Load for AC Timing and output slew Rate 224 13.2 tREFI .224 13.3 Clock Specification 225 13.3.1 Definition for tCK(abs)....... 225 13.3.2 Definition for tcK(avg) ∴225 13.3.3 Definition for tCH(avg) and tCL(avg) 225 13.34 Definition for teRR(nper)…… 225 13. 4 Timing Parameters by Speed Grade 226 13.5 Rounding algorithms 243 13.6 The dQ input receiver compliance mask for voltage and timing(see Figure 211) 13.7 Command, Control, and Address setup Hold, and derating 13.8 DDR4 Function matrix 250 JEDEC Standard no, 79-4B Page 1 DDR4 SDRAM STANDARD (From JEDEC Board Ballot JCB-16-56, formulated under the cognizance of the JC-42 3 Subcommittee on DRAM Memories. Scope This document defines the DDR4 SDRAM specification, including features, functionalities, AC and dC characteristics, packages, and ball/signal assignments. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant 2 Gb through 16 Gb for X4, X8, and X16 DDR4 SDRAM devices. This standard was created based on the DDR3 standards (JESD79-3)and some aspects of the ddR and dDR2 standards JESD79, JESD79-2) Each aspect of the changes for DDR4 SDRAM operation were considered and approved by committee ballot(s). The accumulation of changes into Functional D rporated to prepare this JEDEC Standard, JESD79-4, replacing whole sections and incorporating the these ballots were then scription and operation JEDEC Standard no. 79-4B Page 2 2 DDR4 SDRAM Package Pinout and Addressing 2.1 DDR4 SDRAM Row for x4, x8 and x16 The DDR4 SDRAM X4/x8 component will have 13 electrical rows of balls. Electrical is defined as rows that contain signal ball or power/ ground balls. There may be additional rows of inactive balls for mechanical support The DDR4 SDRAM X16 component will have 16 electrical rows of balls. There may be additional rows of inactive balls for mechanical support. 2.2 DDR4 SDRAM Ball Pitch he DDR4 SDRAM component will use a ball pitch of 0.8 mm by 0.8 mm. The number of depopulated columns is 3 2.3 DDR4 SDRAM Columns for x4X8 and x16 The DDR4 SDRAM X4/x8 and x16 component will have 6 electrical columns of balls in 2 sets of 3 columns. there will be columns between the electrical columns where there are no balls populated. the number of these columns is 3 Electrical is defined as columns that contain signal ball or power/ground balls. There may be additional columns of inactive balls for mechanical support 2.4 DDR4 SDRAM X4/8 Ballout using Mo-207 2 3 456 8 9 DM n, DBl VDD VSSQ TDQS c TDQS t2 VSSQ VSS A NC)T PP VDDQ DQS DQ1VDDQ ZQ B VDDQ DQO DQs t VDD VSS VDDQ DQ4 DQ5 D VSSQ (NC)1 DQ2 DQ3 (NC) VS SSQ DQ7 E SS DQ6 VDDQ (NC) (NC) VDDQ VSS DD (C2 ODT16 ODT CK t CK VDD VSS (CO) CKE Cs n C1) G CKE1 (CS1_n Nc VDD ACT n CAs n RAs n A14 A15 A16 VSS H VREFCA BGO A10 A12 AP BC n BG1 VDD K BAO A4 A3 BA1 VSS RESET n A6 AO A1 A5 ALERT_nL M VDD A8 A2 A9 A7 VPP M A17 SS A11 PAR A13 VDD N Nc NOTE 1 These pins are not connected for the x4 configuration notE 2 TDQS t is not valid for the x4 configuration noTE 3 TDQS C is not valid for the x4 configuration nOtE 4 A17 is only defined for the x4 configuration NOTE 5 These pins are for stacked component such as 3DS For mono package, these pins are Nc NOTE 6 ODT1/CKE1/CS1_n are used together only for DDP NOTE 7 TEN is optional for 8Gb and above. This pin is not connected if ten is not supported

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