pg168-gtwizard.pdfxilinx fpga gt wizard serdes手册用

文件名称: pg168-gtwizard.pdf

所属分类: 硬件开发

开发工具:

文件大小: 11mb

下载次数: 0

上传时间: 2019-10-05

提供者: weixin_********

下载 (11mb)

不能下载？报告错误

详细说明：xilinx fpga gt wizard serdes手册用于Xilinx开发查看sXL|NⅩ ALL PROGRAMMABLEN Reset Sequence Modules for GTH and GTP Transceivers 87 Example design description for gTZ Transceivers.................... 87 Known limitations of the gtz wizard ·····:::.:.:·····.··...·:··.·..···· 95 Known limitations of the wizard 96 Appendix A: Verification, Compliance, and Interoperability Simulation 97 Hardware Testing........................ 97 Appendix B: Migrating and Upgrading Migrating to the vivado design Suite 98 Upgrading in the vivado Design Suite 98 Appendix C: Debugging FindingHelponXilinx.com................ 108 Debug tools∴... 109 Wizard validation 110 Simulation Debug..… 119 Next ste 122 Hardware Debug∴…,………122 Loopback Limitations.,,........ ,,,,,,,,,,,.,.126 GT Debug Using ibeRT........ 126 Debugging Using Serial l/o Analyzer 126 Debugging Using Embedded BERT 127 7 Series gT Wizard hardware validation on the Kc705 Evaluation board 27 Appendix D: Additional Resources and Legal notices Xilinx Resources∴ 145 References 145 Revision History.∴.……∴ 146 Please Read: Important Legal Notices...............,........ 147 7 Series fPgas transceivers wizard v 3. 6 www.xilinx.com Send feedback PG168 November 30 2016 &A XILINX IP Facts Introduction LogiCORE IP Facts Table Core Specifics The 7 series fpgas transceivers wizard Supported Artx③-7, Kintex-7, and virtex⑧-7 FPGAs,and LogiCORETM IP automates the task of creating Device Family(l) Zyng all Programmable Socs HDL wrappers to configure XilinX R7 series Supported User FPGA on-chip transceivers. The wizard Interfaces Not Applicable customization Vivado R Integrated Design Resources Environment(IDE)allows you to configure one Provided with core or more high -speed serial transceivers using Design Files RTL either pre-defined templates supporting Verilog and∨HDL popular industry standards, or from scratch to Example design (Only Verilog is supported for GTZ transceivers) support a wide variety of custom protocols Test bench erilog and VHDL (Only Verilog is supported for GTZ transceivers) Constraints file XDC IMPORTANT: Download the most up-to-date IP Simulation update before using the Wizard None Model Supported S/W Driver(2) icable Features Tested Design Flows(2) Design Entry Vivado Design Suite Simulation For supported simulators, see the Creates customized HDL wrappers to Xilinx Design Tools: Release Notes Guide configure high-speed serial transceivers in Synthesis Vivado Synthesis 7 series fpgas Support Automatically configures analog settings Provided by Xilinx at the Xilinx Support web page Predefined templates are provided for Notes Aurora 8B/10B, Aurora 64B/ 66B, CEI-6G 1. For a complete list of supported devices, see the Vivado IP catalo Display Port, Interlaken, Open Base Station 2. For the supported versions of the tools, see the Architecture Initiative(OBSAI, OC192 Xilinx Design Tools: Release Notes Guide OC48, SRIO, 10GBASE-R, Common Packet Radio interface( CPRi), Gigabit Ethernet, 10 Gb Attachment Unit Interface(XaUi RXAUI and xlaul, otu3, 10Gh Small Form-factor Pluggable Plus(SFP+),Optica Transport Network OTU3, V-by-One, SDI, and others as well as custom protocol using start from scratch 7 Series fPgas transceivers wizard v 3. 6 www.xilinx.com end seedlac PG168 November 30 2016 Product Specification ⅩL|NX ALL PROGRAMMABLEIN Chapter 1 OverⅰeW The 7 series FPGAs Transceivers Wizard (Wizard) can be used to configure one or more Virtex-7, Kintex R-7, ArtiX R-7, and Zyng r-7000 device transceivers. Start from scratch, or use an industry-standard template to configure 7 series fPga transceiver cores. The wizard generates a custom wrapper for the transceivers with all inputs given through the transceiver wizard Vivado IDE In addition, the wizard generates an example design, test bench, and scripts to observe the transceivers operating under simulation and in hardware About the wizard The 7 series FPGAs Transceiver Wizard automates the task of creating hdl wrappers to configure the high-speed serial transceivers in Artix-7, Kintex-7, and Virtex-7 FPGAs The menu-driven interface allows you to configure one or more transceivers using predefined templates for popular industry standards, or by using custom templates,to support a wide variety of custom protocols. The Wizard produces a wrapper, an example design, and a test bench for rapid integration and verification of the serial interface with your custom function The Wizard produces a wrapper that instantiates one or more properly configured transceivers for custom applications(Figure 1-1) 7 Series fPgas transceivers wizard v 3. 6 www.xilinx.com Send feedback PG168 November 30 2016 K XILINX Chapter 1: Overview Customization Wrapper Application Transceiver Ports Ports (Gigabit Transceiver Parameters FG168c1c109101 Figure 1-1: Transceiver Wizard Wrapper The Wizard can be accessed from the vivado design suite For the latest information on this wizard, see the architecture Wizards product information page For documentation, see the 7 series FPGAs Transceivers Wizard page Functional overview Figure 1-2 shows the steps required to configure transceivers using the Wizard. Start the Vivado Ip catalog, select the 7 series FPGAs Transceivers Wizard, then follow the chart to configure the transceivers and generate a wrapper that includes the accompanying example design To use an existing template with no changes, click Generate To modify a standard template or start from scratch, proceed through the wizard and adjust the settings as needed 7 Series fPgas transceivers wizard v 3. 6 www.xilinx.com Send feedback PG168 November 30 2016 K XILINX Chapter 1: Overview Select Protocol Determine Tile Placement Select Reference Clock Source Standard Custom Adjust Parameters As Needed Click Generate Figure 1-2: Wizard Configuration Steps Structure of the Transceiver Wrapper, Example design and Test Bench Figure 1-3 shows the relationship of the transceiver wrapper, example design, and test bench files generated by the Wizard. For details, see Example Design Description for GTX, GTH, and GTP Transceivers, page 82 7 Series fPgas transceivers wizard v 3. 6 www.xilinx.com Send feedback 7 PG168 November 30 2016 K XILINX Chapter 1: Overview Test bench Example Design Core To CSL Scramble it module PMA Modules Clock module Block Sync Descrambler TⅩ RX Buffer Reset Reset Bypass FSM FSM GT Common Frame Gen Multi GT Wrapp RX Data file Transceiver GT Frame Check Common Reset Wrapper Configuration Paramete TX Data File PG168C1_03_101713 Figure 1-3: Structure of the Transceiver Wrapper, Example Design, and Test bench The following files are generated by the wizard to illustrate the components needed to simulate the configured transceiver Transceiver wrapper, which includes Specific serial transceiver configuration parameters set using the Wizard Transceiver primitive selected using the wizard Example design demonstrating the modules required to simulate the wrapper these include FRAME GEN module: Generates a user-definable data stream for simulation analysis 7 Series fPgas transceivers wizard v 3. 6 www.xilinx.com Send feedback PG168 November 30 2016 K XILINX Chapter 1: Overview FRAME CHECK module Tests for correct transmission of data stream for simulation analysis Test bench: Top-level test bench demonstrating how to stimulate the design Feature summary The Wizard has these features Creates customized HDL wrappers to configure transceivers in the Kintex-7 and Virtex-7 FPGAs Predefined templates automate transceiver configuration for industry standard protocols GTX transceivers support Common Packet radio Interface( cPri): 0.6,, 2.4, 3.072, 4.9, 6.144, and 9. 83 Gb/s OC-48:2488Gb/s OC-192:9956Gb/ Gigabit Ethernet: 1. 25 Gb/s Aurora 64B/66B: 12.5 Gb/s Aurora 8B/10B: 6.6 Gb/s Display port: 1.620, 2.7, 5.4 Gb/s 10GBASE-R: 10.3125 Gb/s Interlaken: 4.25, 5.0, 6.25 Gb/s Open Base Station Architecture Initiative(OBSAI): 3.072 Gb/s OBSAI: 6.144 Gb/s 0 Gb Attachment Unit XAUD): 3.125 Gb/s 10 Gb Reduced Attachment Unit(RXAUI): 6.25 Gb/s Serial ATA(Sata): 6.0 Serial RapidIo Gen1: 1.25, 2.5,3.125 Gb/s Serial RapidIo gen2: 1.25, 2.5,3.125, 5.0, 6.25 Gb/s JESD204:3.0,6.0Gb/s 100 Gb Attachment Unit Interface(CAUI): 10. 3125 Gb/s 10GBASE-KR: 10.3125 Gb/s 7 Series fPgas transceivers wizard v 3. 6 www.xilinx.com Send feedback PG168 November 30 2016 K XILINX Chapter 1: Overview Common Electrical Interface( CED)6G-SR: 4.976-6.375 Gb/s 40 Gb Attachment Unit Interface(XLAuI): 10.3125 Gb/s Quad Serial Gigabit Media Independent Interface(QSGMII): 5 Gb/s igh-Definition Serial Digital Interface(HD-SDI)/3 Gb/s Serial Digital Interface (3G-SDI):1.485/2.97Gb/S GTH transceivers support CEI6G-SR:4.976-6375Gb/s Interlaken: 6.25 Gb/s OGBASE-KR: 10.3125 Gb/s OGBASE-R: 10.3125 Gb/s XLAUI: 10.3125 Gb/s CEI-11:9956-11.1Gb/s CAUI: 10.3125 Gb/s OTU4:11.18,12.5,13.1Gb/s CPRI:0.6,1.2,2.4,3.072,4.9,6.144,and9.83Gb/s Gigabit Ethernet: 1.25 Gb/s OC-48:248832Gb/s OC-1929956Gb/s Display Port: 1.620, 2.7, 5.4 Gb/s JESD204 Optical-channel Transport Lane(OTL)3.4: 10.7546 Gb/s QSGMII: 5 Gb/s RXAUI: 6.25 Gb/s XAUI: 3.125 Gb/s Aurora 64B/66B: 12.5 Gb/s Aurora 8B/10B: 6.6 Gb/s Serial RapidIo Gen2: 1.25,, 3.125, 5.0 Gb/s 7 Series fPgas transceivers wizard v 3. 6 www.xilinx.com Send feedback 10 PG168 November 30 2016

(系统自动生成,下载前可以参看下载内容)