TI高精度实验室-压摆率 2.pdf.pdfTI高精度实验室-压摆率 2.pdfpdf,TI高精度实

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详细说明：TI高精度实验室-压摆率 2.pdfpdf,TI高精度实验室-压摆率 2.pdfBody Effect on Slew Rate Gate Drain ource Body P+ N-Well P-Substrate Body Capacitance 20pF 3 TEXAS INSTRUMENTS o Remember from the first slew rate video that each input pin of an op-amp is connected to a transistor let s assume that these transistors are pmos, or P-type MOsFET. o Looking at a cross-section of a Pmos we see that the body is a deposit of n-type material inside the p-type substrate. a p-type drain and source are then deposited inside the n-well. a diode is formed between the body and substrate simply due to the existence of a p-n junction the diode is normally reverse-biased and has some amount of internal capacitance Changing the common-mode voltage, which is the voltage across the p-n junction, will affect the amount of capacitance since the p-n junction s depletion region width will change ●在压摆率的视频教程1中,我们提到运放的每个输入引脚都是连接到晶体管的。我们此处偎假设晶体管为PMOS,即P型 MOSFET ●图屮所示为典型的PMOS横截面,它在P型的硅基片上嵌入了N型井材料作为衬底,在对底两端各嵌入了P型的源极和漏极。从图中可见,在P型硅基片和N型衬底之间会形成一个二极管。通常这个二极管是反偏的,当改变芯片工作时的共模电压,即改变二极管RN结两端电压时,因为pn结耗尽层宽度变化,结电容大小也会发生变化 Body Effect on Slew Rate Vcc INPUT 100pA 50HA Vin- Off On Bod Cc Cap 20pF 工 20pF Rapid Vin+ change on Vout input signal OUT 50μA 中 TEXAS INSTRUMENTS o Let s go back to the input stage of an op-amp to see the implications that body capacitance has on slew rate o Like in the previous video, we apply a large- signal step across the op-amps input pins. The transistor on the left is off, and the transistor on the right is fully on, so all input stage current lINPUT flows through the right transistor for maximum slew rate. However, the body capacitance to ground provides a new current path and reduces the amount of current ioUt flowing through the miller capacitance CC. This reduced lOUt decreases the effective slew rate of the amplifier since the voltage across a capacitor changes linearly with constant current o In this example, the body capacitance and miller capacitance are both equal to 20pF, SO IOUT will become half of lINPUT as long as the common mode voltage is not constant. In this example the effective slew rate of the amplifier is also cut in half since slew rate is equal to lout/Cc. Note that the body capacitance will charge to the common mode voltage. Thus, if the common mode voltage is kept constant, as in the case of the inverting configuration the body capacitance Will not effect the slew rate ●我们重新回顾一下运放的输入级,来看看体效应电容对压摆率的影响 ●和前面的视频教程一样,我们在运放输入引脚之间施加一个大阶跃信号。图中左边的PMOS截l,右边PMOS导通,从而输入级的所有电流 linput从右边PMoS流过造成lout饱和,运放输出达到压摆率上限。 ●然而,一端接地的体效应电容为lout提供了另一条支路,使得流入密勒电容的电流减小。因为密勒电容两端的电压和流经电容的电流呈线性关系,所以体效应电容造成的分流使运放的压摆率降低。在这个例了中,体效应电容和密勒屯容都等于20pF,所以lout是 linput的半。根据压摆率=out/Cc可知,运放的压摆率也是没有体效应电容时的一半。通过充电,体效应电容两端电压最后会等于共模电压,当运放接成反相放大电路时,如果共电压保持恒定,输入电压将不会影响压摆率 Settling Time INPUT: DIGITAL CHANGE OR ANALOG STEP s OUTPUT RESPONSE ERROR BAND 2 SETTLING TIME 5 TEXAS INSTRUMENTS Let s now move on to discuss settling time e Settling time is the time required for the amplifier s output to reach and stay within a certain error band after a large -signal step is applied to the input the error band can either be specified in terms of percentage or number of lSBs (for an adc with a specified number of bits) o Because the input is a large-signal step the amplifier is in slew rate limit. The tighter the error band is(i.e. smaller error percentage), the longer the settling time will be. Capacitance, closed loop gain, and loading will also effect settling time ●下面我们来讨论建立时间。 ●运放建立时间被定义如下:从给运放输入端施加·大阶跃信号起,到输出信号进入并稳定在一定误差带内为止的时间,这一误差带可以是最终稳定值的百分比或者是模数转换系统中的最小有效位。 ●因为输入是大阶跃信号,运放输出会受压摆率限制,误差带的范围越窄,比如更小的百分比,会造成建立时间将越长。电容、闭环增益和负载都会影响建立时间。 Settling Time VS Closed-loop Gain SETTLING TIME VS CLOSED-LOOP GAIN 0.01% 0.1% 0.1 100 Closed-Loop Gain (VM 6 TEXAS INSTRUMENTS o In many op-amp data sheets, the settling time vs. closed-loop gain is given as a plot such as the one shown here. Again, settling time is longer for a tight error band (for example, 0.01% compared to 0. 1%. This should make intuitive sense Settling time also increases as gain increases. this is because the op-amps loop gain decreases as closed loop gain increases. Remember, loop gain, or the difference between open-loop gain and closed-loop gain is what s used by the op-amp to correct for errors. having less loop gain makes it more difficult for the op-amp to settle quickly 像这幅图一样,许多运放的数据于册都会给出建立时间和闭环增益的关系这里仍然要强调,建立时间会随着误差带变窄而延长,这是最基本的建立时间也会随着增益的增大而延长。这是因为运放内部的环路增益会随运放闭环增益的增加而降低。需要注意的是,运放内部的环路增益和运放的丌环増益、运放的闭环增益都是不冋的,它被用来校正运放的误差。降低环路增益会使运放的建立时间延长。 Simulating Settling Time-OPA827 FREQUENCY RESPONSE Cain-Bandwidth Product G BW MHz Seting t ime,±001% 550 Edt View Process Hep 0.00 c1100n J1 0PA327 c2130n C31000 VOUT vI 18 V2 18v 4,↑4 14326m 7 中 TEXAS INSTRUMENTS o We can very easily simulate the settling time of an op-amp using tINA-TI'S transient analysis function. In order to do this, it is important to closely follow the data sheet test conditions, such as the step size, gain configuration, and load capacitance o In this case we are testing the oPA827 in a gain of -1, with a 10V step input and 100pF of load capacitance 我们可以使用TNA-T里的瞬态分析功能,很方便的仿真运放的建立时间。为了保证仿真结果,我们要尽量使仿真条件和数据手册上的测试条件样, 比如输入阶跃大小,外围电路,负载电容等。 ●在这里,我们对OPA827的建立时间进行仿真,条件如卜:反相放大,闭坏增益为1,输入10V阶跃信号,100pF负载电容。 Simulating Settling Time- Large-signal Output slew noname- R result19 Large-signal Ele Edt yew Process Help step input Output settles 1000 1001 VOUT Settling time includes the slew and 143.26m 0.00 oOu 2.00u settling. We Time(s) will zoom in TA res:)TR reeul 4) TR reau 5 TR reel 6 /TR tesut17) TR tecla TR resut191 ,. on settling region Step input applied at1μs 中 TEXAS INSTRUMENTS Let's take a closer look at the transient analysis of the oPA827 settling o Please note that settling time includes both the time required for the output to slew as well as the time to settle within the specified error band o The time required to settle within of the error band where we see the overshoot and damping oscillations) is difficult to see on this plot due to the time scale, so we will zoom in on the error band region on the next few slides ●图中显示了OPA827建立时间的瞬态分析结果 ●建立时间包含了两部分,一是输出电压的摆动时间,二是进入并稳定在误差范围内的时间。 ●输出电压稳定在误差范围内的细节在此图中无法观察,我们将对其进行放大, 并在后面几张幻灯片中进行分析。 Tina-TITM Post-processor Post-processor X Can Bult in nuncio (o! Tn resul: 14 Tn resu!: 15 Tn resl: lC Tl resull17 T1 resulll) TRrceull1 Create limits for +/-0.01% 9.999Vand10.001V 9 中 TEXAS INSTRUMENTS o Before we zoom in on the settling region though, let s first set up a representation of the error bands for easy visual analysis o this can be done using the tina s post-processor function by adding horizontal lines for the vout values at +0.01% of the ideal since the ideal value is 10V our error band values are 9.999v and 10.001V ●在放大观察建立时间之前,我们先来设置最终要求的误差允许范围,这样会更易于观察和分析。 ●通过点击TNA中的 Post-processor图标,我们在vout上方和下方添加两条水平基准线作为误差允许范围,他们到vout的终值相距0.01%,因为νout的最终值为10V,所以这里误差允许范围是099y到10001V。

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