Improving Execution Performance on SPI Flash of NU

文件名称: Improving Execution Performance on SPI Flash of NUC505.pdf

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详细说明：AN_0011_NUC505_Series_Improving_Execution_Performance_on_SPI_FlashnUVOTon AN0011 Introduction BootTemplate Oct12,2015 Page 3 of 24 Rev 1.00 nUVOTon AN0011 Memory Models Oct12,2015 Page 4 of 24 Rev 1.00 nUVOTon AN0011 oct12,2015 Page 5 of 24 Rev 1.00 nUVOTon AN0011 BootTemplate/CriticalonSRAM Fibonacci Fibonacci Oct12,2015 Page 6 of 24 Rev 1.00 nUVOTon AN0011 LP CoM1-PaTTY 回区 NUCS05 Series Demo Sample R16cE西veeE。tbe五nSRA(Dx20000000)王E王王 nett upe hand1的g, Load Fibonacci2() in SRAM (Ox20000825 ∵ec1t1 Fibonaccil(500000) (on SPI Flash) take=504Q (ms) Fibonacci(500000) (on SRAM) takes 60 (ms) BootTemplate/criticalonSRAM BootTemplate/ criticalonsRaM #主 f defined( CC ARM) extern uint32 t Vectors[l extern uint32 t Vectors size[] extern uint32_t ImageSSER_ VECTOR2$SZISSBase[] memcpy((void * ImageSSER VECTOR2SSZIS$Base, (void *)Vectors, (unsigned int) Vectors size) SCB->VTOR =(uint32 t) ImagessER VECTOR2SSZI$SBase; Oct12,2015 Page 7 of 24 Rev 1.00 nUVOTon AN0011 #elif defined ICCARM pragma section =VECTOR2 extern uint32 t Vectors extern uint32 t Vectors size[]j memcpy((void *)section begin VECTOR2"),(void *)Vectors,(unsigned int) Vectors size); SCB->VTOR =(uint32 t)section begin( VECTOR2"); #endif ER STARTUP +0 startup nuc505Series o(RESET, +First) ER RO +0 *(+RO) Relocate vector table in SRAM for fast interrupt handling ER VECTOR2 9×2999999 EMPTY ex99999489 Critical code in SRAM for fast execution. Loaded by ARM C library at startup ER FASTCODE INIT 0x20000400 clk. o(+RO); CLK SetcoreClock() may take a long time if it is run on SPI Flash ER RW +0 *(+R) Critical code in SRAM for fast execution. Loaded by user ER FASTCODE UNINIT +0 OVERLAY * fastcode oct12,2015 Page 8 of 24 Rev 1.00 nUVOTon AN0011 LR RAM 9×209109099x09910999 ERz工+9 (+Z工) The following is an example of iar linker configuration file for such model. Portions related to critical code /data including vector table are highlighted define symbol ICFEDIT_intvec_start=0x00000000 *-Memory Regions-* define symbol ICFEDIT region RoM start define symbol_ region ROM end 0X001FFFFF define symbol ICFEDIT region_ RAM start =6X26908888; define symbol ICFEDIt region RAM end 0X2001FFFF; /*-S1zeS-* define symbol ICFEDiT size stack =x488 define symbol ICFEDIT size heap =B×880; define memory mem with size=4G; define region ROM region mem: from ICFEDIT_ region_ ROM_start to ICFEDIT region ROM end]3 define region RAM region =mem: [from ICFEDIT region RAM start to ICFEDIT region RAM end]j define block stack with alignment =8, size =ICFEDIT size stack) define block heap with alignment =8, size ICFEDIT size heap define block vector2 with alignment =8, size = 0x400 initialize by copy readwrite, readonly object clk.0; initialize manuall section fastcode do not initialize section . noinit j; place at address mem:ICFEDIT_intvec_starti readonly section . intvec place in ROM region i readonly i place at start of RAM region I block VECTOR2 i place in RAM region i readwrite, block CSTACK, block HEAP oct12,2015 Page 9 of 24 Rev 1.00 nUVOTon AN0011 maino init/startup post-init/startup init/startup post-init/startup init/start init/startup post init/startup Init/startup Post-init/startup Oct12,2015 Page 10 of 24 Rev 1.00

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