STM32 F3产品技术培训-16.供电模块及功耗模式.pdfSTM32 F3产品技术培训-16.供

文件名称: STM32 F3产品技术培训-16.供电模块及功耗模式.pdf

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详细说明：STM32 F3产品技术培训-16.供电模块及功耗模式SRM32F30X Power Supply s Power Supply Schemes VDD=2.0 to 3.6V: External Power Supply for Vppa domain lOsor VDD=1.8+/-8%:%: External Power AD converter Supply for l/Os with internal regulator is OFF) D/A converter COMP Temp. sensor DDA Reset block SSA VDDa=2.0 to 3.6 V: External Analog Power PLL supplies for ADC, DAC, Reset blocks, RCs and Von domain Va domain PLL 10 Rings STANDBY circuit i DAC working only if VDDa >=2. 4V (Wake-up logic WWWDG, RTC, LSE Core VBAT =1.65V to 3.6 V: For Backup domain crystal 32K osc, Memories RCC CSR Digital when VDD is not present. peripherals Voltage Regulator Power pins connection: VDD and Vdda can be provided by a separated power Low Voltage detector supply source Backup domain VSS and Vssa must be tight to ground LSE crystal 32K osc BAT BKP registers RCC BDCR register RTC life. augmented SRM32F37X Power Supply a Power Supply Schemes dpa domain VDD=2.0 to 3.6 V: External Power Supply for l/Os(or VDD=1. 8+/-8%: % External Power AD converter Supply for l/Os with internal regulator is OFF.) DIA converter SDADC12Vn■ COMP SDADC3 Vpp Temp. sensor SDADC123Vss Reset block PLL VDDa= 2.0 to 3.6 V: External Analog power SDADCS supplies for ADC, DAC, Reset blocks, Rcs and ssA口 PLL dp domain Va domain i ADC and dac working only if VDDA >=2.4 V 1/0 Rings STANDBY circuitry VBaT =1.65V to 3.6 V: For Backup domain when (Wake-up logic, WWWDG. RTC, LSE Core VDD is not present crystal 32K osc, Memories RCC CSR) Digita SDADCX_ VDD=2. 2 to 3.6V: External Analog peripherals Power supplies for SDADCs with Voltage Regulator Power pins connection: Low Voltage detector VDD and Vdda can be provided by a separated power Backup domain supply source LSE crystal 32K OSc BKP registers VSS, VSSA and SDADCX VSS must be tight to ground BAT RCC BDCR register The sd1 sd2 vdd and sd3 vdd can be different from vdd RTC VDDa and from one another life. augmented Power Sequence 5 When VDd power supply source is different from VDDa power supply source(VDD< VDDA) The VDDa voltage level must be always greater or equal to the VDD VOltage During power-on, the VDDA must be provided first(before VDD) During power-off, it is allowed to have temporarily VDD> VDDA, but the voltage difference must be <0. 4V could be maintained by an external Schottky diode When SDADCX power supply is different from VDDA, VDD power supply and from one another SDADCX VDD Threshold 7 Can be used to generate a warning message and/or put the mcu into a safe state life. augmented Backup Domain g Backup Domain contains Low power calendar rtc (Alarm, periodic wakeup from Stop/Standby) 64 and 128 Bytes Data rtc registers in STM32F30X and sTM32F37x respectively Separate 32kHz OSc LSE) for RTC Backup Domain RCC BDCR register RTC clock source selection and enable LSE config power switch RCC BDCR 32KHZ OSc SE Reset only by rtc domain rESet Wakeup WWDG Logic VBAT independent voltage supply RTC TAMPX RTC+ 64(or 128 )Bytes Data Automatic switch-over to VBaT when Vdd goes lower than pdr level No current sunk on VBAT When VDD present 2 X Tamper events detection: resets all user backup registers Time stamp event detection life. augmented LoW Power Modes(1/4)1o SLEEP Mode: Core stopped, peripherals kept running Entered by executing special instructions WFI (Wait For Interrupt Exit: any peripheral interrupt acknowledged by the Nested Vectored Interrupt Controller(NVIC) WFE (Wait For Event) An event can be an interrupt enabled in the peripheral control register but NoT in the Nvic or an EXTI line configured in event mode Exit: as soon as the event occurs No time wasted in interrupt entry/exit Two mechanisms to enter this mode Sleep Now: MCU enters SLEEP mode as soon as WFI/FE instruction are executed Sleep on Exit: MCU enters SLEEP mode as soon as it exits the lowest priority ISR To further reduce power consumption you can save power of unused peripherals by gating their clock life. augmented

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