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STM32L4循环冗余校验模块(CRC)介绍.pdf
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上传时间: 2019-09-14
详细说明：STM32L4循环冗余校验模块(CRC)介绍CRC Introduction 2/213
Advanced features
Programmable parameters
Fully Programmable ODD Polynomial
By default uses CRC-32(Ethernet) polynomial: 0X4C11DB7
Uses a fully programmable ODD polynomial with programmable size(7, 8, 16, 32 bit)
Programmable polynomial size(7, 8, 16, 32 bits)
Programmable reset initial value(default=OXFFFF FFFF)
Reversibility option on lo data
Input data can be reversed by 8, 16, 32 bit
Example if input data Ox C4D is used for CRC calculation as
0X58 D43CB2 with bit-reversal done by byte
OxD458B23C with bit-reversal done by half-word
0xB23CD458 with bit-reversal done on the full word
Output data can be reversed in 32-bit(output register)
Example on output data 0X11223344
0x1122344回00010do100noon000od
0x22CC4488 00100010110011000100010010001000
life, augmented
CRC Operation 1/214
Operation
Each write operation to the data register creates a combination of the previous
CRC value(stored in CRC DR)and the new one. CRC computation is done on the
whole 32-bit data word or byte by byte depending on the format of the data being
written
The duration of the crc computation depends on input data width:
4 AHB clock cycles for 32-bit
2 AHB clock cycles for 16-bit
1 AHB clock cycles for 8-bit
Polynomial can be changed after finishing current CRC calculation(or after CRC
rese
The input and output data can be bit reversed to manage the various endianness
schemes(REV IN[1: 0], REV OUT bits)
life, augmented
CRC Operation 2/215
AHB BUS
32-bit(read access)
Data register(Output)
Reset/nitial value
CRC computation engine
Polynomial
Bit reversal (in/out
Data register(Input) with buffer
32-bit( write access)
One Single in/out 32-bit data register for intuitive Firmware operation
Writes can be done by dMa while CPU is in Sleep mode
Low power Operation( back to back) and Free CPU for important MiPS tasks
life, augmented
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