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上传时间: 2019-09-07
详细说明：stm32 MCU user manual, STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and
STM32F107xx advanced Arm®-based 32-bit MCUsRM0008
Contents
5.2.1 Power on reset(POR)/power down reset(PDR)
..70
5.2.2 Programmable voltage detector(PVD)
70
5.3 LOW-power modes ........
,,,,72
5.3.1 Slowing down system clocks
,,,,,72
5.3.2 Peripheral clock gating
5.3.3 Sleep mode
5.3.4 Stop mode
74
5.3.5 Standby mode
76
5.3.6 Auto-Wakeup(AWU) from low-power mode
5.4 Power control registers
77
5.4.1 Power control register(PWR_ CR
5.4.2 Power control/status register(PWR_ CSR)
...79
5. 4.3 PWR register map
.80
Backup registers(BKP)∴.………
81
6.1 BKP introduction
6.2 BKP main features
88
6.3 BKP functional description
82
6.3.1 Tamper detection
6.3.2 RTC calibration
::::::
82
6. 4 BKP registers
83
6.4.1 Backup data register x(BKP_DRX)(x=1. 42)
翻
6.4.2 RTc clock calibration register(BKP_RTCCR)
6.4.3 Backup control register(BKP_CR)
84
6.4.4 Backup control/status register(BKP CSr)
...84
6.4.5 BKP register map
...85
LoW-, medium-, high- and XL-density reset and clock
control(RCC)...............
90
7.1 Reset,,,,,,,,,,,,,
90
7.1.1 System reset
90
7.1.2 Power reset
7.1.3 Backup domain reset
..92
7.2 Clock
92
72.1
HSE Clock
94
7.2.2 HSI clock
95
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Contents
RMO008
7.2.3PLL
7. 2.4 LSE clock
96
7.2.
LSI clock
96
7. 2.6 System clock (SYSCLK) selection
97
7. 2.7 Clock security system(CSS
..97
7.2.8 RTC clock
98
72。 Watchdog clock
98
7.2.10 Clock-out capability
...98
7.3 RCC registers
99
7.3.1 Clock control register(RCC_ CR)
7.3.2 Clock configuration register(RCC CFGR
7.3. 3 Clock interrupt register(RCC_CIR)
104
7.3.4 APB2 peripheral reset register(RCC_APB2RSTR)
106
7.3.5 APB1 peripheral reset register(RCC_APB1RSTR)
109
7.3.6 AHB peripheral clock enable register(RCC_AHBENR)
111
7.3.7 APB2 peripheral clock enable register(RCC_APB2ENR)
112
7. 3.8 AP B1 peripheral clock enable register (RCC_APB1ENR)
7.3. 9 Backup domain control register(RCC BDCR)
118
7. 3.10 Control/status register(RCC- CSr)
..119
7. 3.11 RCC register map
.121
Connectivity line devices: reset and clock control (RCC)
123
8.1 Reset,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,123
System reset
123
8.1.2 Power reset
124
8.1.3 Backup domain reset
125
8.2 Clocks
125
8.2.1
HSE Clock
127
8.2.2 HSI clock
128
8.2 3 PLLs
11
,,129
8. 2. 4 LSE clock
129
8.2.5 LSI clock
.130
8.2.6 System clock (sYSCLK) selection
,,.130
8.2.7 Clock security system (CSS
131
8.2.8 RTC clock
8.2.9 Watchdog clock
131
8.2.10 Clock-out capability
.132
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RM0008
Contents
8.3 RCC registers
132
8.3.1 Clock control register(RCC_ CR)
.,,132
8.3.2 Clock configuration register(RCC- CFGr)
134
8.3.3 Clock interrupt register (RCC_CIr)
137
8.3.4 APB2 peripheral reset register(RCC_APB2RSTR)
141
8.3.5 APB1 peripheral reset register(RCC_APB1RSTR)
142
8.3.6 AHB Peripheral Clock enable register(RCC_AHBENR)
145
8.3.7 AP B2 peripheral clock enable register(RCC APB2ENR)..... 146
8.3.8 APB1 peripheral clock enable register(RCC_ APB1ENR)..... 148
8.3.9 Backup domain control register(RCC_ BDCR)
...150
8.3.10 Control/status register(RCC__CSR)
152
8.3.11 AHB peripheral clock reset register (RCC_AHBRSTR
153
8.3. 12 Clock configuration register2(RCC_CFGR2)
154
8.3.13 RCC register map
156
General-purpose and alternate-function VOs
( GPlOs and FLos)∴
159
9.1 GPlO functional description
159
9.1.1 General-purpose I/O(GPIO)
9.1.2 Atomic bit set or reset
161
External interrupt/wakeup lines
162
9.1.4 Alternate functions(AF)
,,.162
9.1.5 Software remapping of /o alternate functions
,.....162
9.1.6 GPlO locking mechanism
162
9.1.7 Input configuration
9.1.8 Output configuration
163
9.1. 9 Alternate function contiguration
164
9.1.10 Analog configuration
165
9. 1.11 GPlo configurations for device peripherals
,,,166
9.2 GPIO registers
171
9.2.1 Port configuration register low(GPIOx_ CRL)(X=AG)
171
9.2.2 Port configuration register high(GPIOX_CRH)(X=AG
172
9.2.3 Port input data register (GPIOX_IDR)(X=AG)
172
9.2.4 Port output data register(GPIOX_ODR)(X=AG)
173
9. 2.5 Port bit set/reset register(GPIOX_BSRR)(X=A.G)
173
9. 2.6 Port bit reset register(GPlOX_BRR)(X=AG
.,,174
9.2.7 Port configuration lock register(GPIOx LCKR)(x=A G)..... 174
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Contents
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9.3 Alternate function V0 and debug configuration(AFlO)
175
9.3.1 Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15..175
9.3.2 Using OSC_IN/OSC_OUT pins as GPIO ports PDO/PD1
175
9.3.3 CaN1 alternate function remapping
176
9.3.4 CAN2 alternate function remapping
,,176
9.3.5 JTAG/SWD alternate function remapping
176
9.3.6 ADC alternate function remapping
9.3.7 Timer alternate function remapping
,,,,178
9.3.8 USART alternate function remapping
180
9.3. 9 12C1 alternate function remapping
181
9.3.10 SPll alternate function remapping
181
9.3.11 SP13/12S3 alternate function remapping
9.3. 12 Ethernet alternate function remapping
181
9.4 AFIO registers
183
9.4.1 Event control register(AFIO_EVCR)
183
9.4.2 AF remap and debug wo configuration register(AFIO_MAPR )......184
9. 4. 3 EXternal interrupt configuration register 1(AFIO_EXTICR1)
...191
9.4.4 External interrupt configuration register 2(AFIO_EXTICR2).... 19
9. 4.5 External interrupt configuration register 3(AFIO_EXTICR3).... 192
9.4.6 EXternal interrupt configuration register 4(AFIO_EXTICR4
192
9. 4.7 AF remap and debug lo configuration register2 (AFIO_MAPR2.. 193
9.5 GPIO and AFlO register maps
194
10
Interrupts and events
197
10.1 Nested vectored interrupt controller(NVIC)
197
10.1.1 Sys Tick calibration value register
.197
10.1.2lnte
and exception vectors
198
10.2 External interrupt/event controller(EXTI)
207
10.2.1 Main features
207
10.2.2 Block diagram
207
10.2.3 Wakeup event management
208
10.2.4 Functional description
208
10.2.5 External interrupt/event line ma
0. 3 EXTI registers
211
10.3.1 Interrupt mask register(EXTI_IMR)
...211
10.3.2 Event mask register(EXTI_EMR)
,,21
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Contents
10.3.3 Rising trigger selection register(EXTI_RTSR)
212
10.3. 4 Falling trigger selection register (EXTI_FTSR)
212
10.3.5 Software interrupt event register (EXTI SWIEr)
213
10.3.6 Pending register(EXTI_PR
10.3.7 EXTI register map
面
214
Analog-to-digital converter(ADC)
215
11.1 ADC introduction
215
11.2 ADC main features
....216
11.3 ADC functional description
....216
11.3.1 ADC on-off control
218
11.3.2 ADC clock
..218
11.3.3 Channel selection
218
1.3.4 Single conversion mode
219
11.3.5 Continuous conversion mode
.219
11.3.6 Timing diagram
219
3.7 Analog watchdog
220
11.3.8 Scan mode,,,,,,,,,,,,,,,,,,,.
221
11.3. 9 Injected channel management
221
11.3.10 Discontinuous mode
..222
11.4 Calibration
223
11.5 Data alignment
224
11.6 Channel-by-channel programmable sample time..........225
11.7 Conversion on external trigger
225
11.8 DMA request
,,227
11.9 Dual ADC mode
228
11. 9.1 Injected simultaneous mode
230
11.9.2 Regular simultaneous mode
230
11.9.3 Fast interleaved mode
11.9.4 Slow interleaved mode
231
11.9.5 Alternate trigger mode
232
11.9.6 Independent mode
233
11. 9.7 Combined regular/injected simultaneous mode
23
11. 9.8 Combined regular simultaneous +alternate trigger mode..... 233
11. 9.9 Combined injected simultaneous interleaved
,,,,,,,,,,234
11.10 Temperature sensor
235
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Contents
RMO008
11 11 ADC interrupts
236
11.12 ADC registers...,,,,.,,.,,.…,237
11.12.1 ADC status register (ADC_Sr)
11.12.2 ADC control register 1(ADC_CR1)
238
11.12. 3 ADC control register 2(ADC CR2)
240
11.12.4 ADC sample time register 1(ADC_ SMPR1).......... 244
11.12.5 ADC sample time register 2(ADC SMPR2
245
11.12.6 ADC injected channel data offset register x(ADC_JOFRx)(x=1.4). 245
11.12.7 ADC watchdog high threshold register(ADC_HTR)
.246
11.12.8 ADC watchdog low threshold register(ADC_LTR)
24
11.12. 9 ADC regular sequence register 1(ADC_SQR1)
,,,247
11. 12.10 ADC regular sequence register 2(ADC_SQR2)
248
11.12. 11 ADC regular sequence register 3(ADC SQR3)
249
11.12. 12 ADC injected sequence register (ADC_JSQR)
...,,250
11.12.13 ADC injected data register X(ADC_JDRx)(X=1.4)
25
11.12. 14 ADC regular data register (ADC_DR)
11.12. 15 ADC register map
....252
12
Digital- to-analog converter(DAC)∴……….
254
12.1 DAC introduction,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,254
12.2 DAC main features
254
12.3 DAC functional description
■■■
,,,,,,,,256
12.3.1 DAC channel enable
.....256
12.3.2 DAC output buffer enable
.256
12.3.3 Dac data format
256
12. 3, 4 DAc conversion
257
12.3.5 DAC output voltage
258
12.3.6 DAC trigger selection
258
12.3.7 DMA request
259
12.3. 8 Noise generation
259
12.3.9 Triangle-wave generation
260
12.4 Dual dac channel conversion
26
12.4.1 Independent trigger without wave generation
261
12.4.2 Independent trigger with same LF SR generation
262
12.4.3 Independent trigger with different LF SR generation
.262
12.4.4 Independent trigger with same triangle generation
,.262
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RM0008
Contents
12.4.5 Independent trigger with different triangle generation
.263
12.4.6 Simultaneous software start
263
12.4.7 Simultaneous trigger without wave generation
263
12.4.8 Simultaneous trigger with same LFSR generation
,,.264
12.4. 9 Simultaneous trigger with different LFSR generation
,264
12.4.10 Simultaneous trigger with same triangle generation
264
12. 4.11 Simultaneous trigger with different triangle generation
.265
12.5 DAC registers
■■■
265
12.5. 1 DAC control register (DAC_CR)
265
12.5.2 DAC software trigger register(DAC SWTRIGR)
.268
12.5.3 DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1)
,,,..,269
12.5. 4 DAC channel1 12-bit left aligned data holding register
DAC DHR12L1)
269
12.5.5 DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1)
,,,,.,.269
12.5.6 DAC channel2 12-bit right aligned data holding register
(DAC_DHR 12R2
270
12.5.7 DAC channel2 12-bit left aligned data holding register
(DAC_DHR12L2
270
12.5. 8 DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8 R2)
270
12.5. 9 Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD)
271
12.5.10 DUAL DAC 12-bit left aligned data holding register
(DAC_DHR12LD)
,,,,271
12.5.11 DUAL DAC 8-bit right aligned data holding register
(DAC_DHR8RD)
272
12.5. 12 DAC channell data output register(DAC_DOR1
272
12.5.13 DAC channel2 data output register(DAC DOR2)
,272
12.5. 14 DAC register ma
.273
Direct memory access controller(DMA)
274
13.1 DMA introduction
274
13.2 DMA main features
274
13.3 DMA functional description
276
13.3.1 DMA transactions
..276
13.3.2 Arbiter
277
13.3.3 DMA channels
,,,,277
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Contents
RMO008
13.3.4 Programmable data width, data alignment and endians
279
13.3.5 Error management
280
13.3.6 Interrupts
28
13.3.7 DMA request mapping
280
13.4 DMA registers
284
13.4.1 DMA interrupt status register(DMA_ISR)
284
13.4.2 DMA interrupt flag clear register(DMA_IFCR
285
13.4.3 DMA channel x configuration register(DMA_CCRx)(x=1.7
Where x
pannel number
13. 4.4 DMA channel x number of data register(DMA_ CNDTRx)(x=1.7,
where x= channel number)
287
13.4.5 DMA channel x peripheral address register(DMA_CPARX)(x=1.1,288
where x= channel number)
13.4.6 DMA channel x memory address register(DMA_CMARx)(x=1.7,
where x=channel number)
288
13.4.7 DMA register map
.289
14
Advanced-control timers (tiM1 and TM8)
292
141 TiM1 and tim introduction
292
14.2 TIM1 and tim8 main features
..293
14.3 TIM1 and TIM8 functional description
....295
14.3.1 Time-base unit
.295
14.3.2 Counter modes
.297
14.3.3 Repetition counter
306
14.3.4 Clock selection
.308
14.3.5 Capture/ compare channels
.311
14.3.6 Input capture mode
314
14.3.7 PWM input mode
315
14.3.8 Forced output mode
316
14.3.9 Output compare mode
...316
14.3.10 PWM mode
.317
14.3.1 1 Complementary outputs and dead- time insertion
,32
14.3.12 Using the break function
322
14.3.13 Clearing the OCX REF signal on an external event
..326
14.3. 14 6-step PWM generation
.327
14.3.15 One-pulse mode
328
14.3.16 Encoder interface mode
..329
14.3.17 Timer input XOR function
,.,...332
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