x86中断和异常处理.pdfx86中断和异常处理文档，描述了x86处理器架构的中断处理流程Sourc

文件名称: x86中断和异常处理.pdf

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详细说明：x86中断和异常处理文档，描述了x86处理器架构的中断处理流程Sources: Hardware Interrupts Hardware Interrupt Types 工NTR Non-Maskable Interrupt PIC Never ignored X86 CPU 8259A N工 INTR Maskable gored when IF is o PIC: Programmable Interrupt Controller (8259A) Has 16 wires to devices (irQ0-irQ15) Can be programmed to map irQo-15> vector number Vector num ber is signaled over INTR line In Jos/lab4 vector←(RQ#+ OFFSET Sources: Software-generated Interrupts Programmed Interrupts x86 provides INt instruction Invokes the interrupt handler for vector N(0-255) JOS: We use 'INT 0x30 for system calls Software Exceptions Processor detects an error condition while executing an instruction Ex: divl eax % eax Divide by zero if EAX=0 EX:movl %ebx, %eax Page fault or seg violation if EAX is un-mapped virtual address EX: jmp $BAD JMP General Protection Fault gjmp'd out of cs) Enabling /Disabling Interrupts Maskable Hardware Interrupts Clearing the if flag inhibits processing hardware interrupts delivered on the intR line Use the sti (set interrupt enable flag)and cll(clear interrupt enable flag) instructions IF affected by: interrupt/task gates, POPF, and IRET Non-Maskable Interrupt Invoked by NMI line from PIC Always Handled immediately Handler for interrupt vector 2 invoked No other interrupts can execute until NMi is done DT: Interrupt Descriptor Table IDTE Table of 256 8-byte entries(similar to the GDt) In JoS: Each specifies a protected entry-point into the kernel Located anywhere in memory IDTR Register 47 161 IDTR register: iDT Base Address IDT Limit Stores current Dt Lidt instruction? Interrupt Descriptor Table (IDT) Loads idtr with address and size Gate for Interrupt #n (n-1)=8 of the idt Takes in a linear address Gate for Interrupt #3 Gate fo Interrupt #2 Gate for Interrupt +1 DT Entries Destination IDT Code Segment Interrupt Gate 31 1615141312 54 Interrupt Offset 31.16 F|F0D110000 Offset Procedure Interrupt Interrupt or Vector Trap gate 31 1615 0 Segment selector Offset 15.0 Selector Segment Selector for dest code segment Offset offset to procedure entry point Segment Selector Segment Present Flag GdT or LDT DPL Descriptor Privilege leve Base Ibit 40] 0= interrupt gate; 1= trap gate S Size of gate: 1=32 bits;0=16 bits Address segment Descriptor JOS: Interrupts and Address spaces Jos approach tries to minimize segmentation usage so ignore segmentation issues with interrupts Priority Level switch CPL is low two bits of Cs(11=kernel, 00=user) Loading new Cs for handler can change cpl JOs interrupt handlers run with kernel CPL Addressing switch No address space switch when handler invoked Paging is not changed However in: Kernel va regions now accessible Stack Switch (User Kernel) stack switched to a kernel stack before handler is invoked TSS: Task State segment 31 15 Specialized Segment for hardware yO Map Base Address LDT Segment Selector supported multi-tasking GS (we don't use this x86 feature) DS CS TSS Resides in memory S 72 EDI ESI 64 TSS descriptor goes into GDT EBP ESP (size and linear address of the tss) EBX EDX Ltr(GD Tss) loads descriptor ECX 44 EAX 40 EFL EIP In JOss Tss CR3(PDBR) SS2 24 SSO: ESPo kernel stack used ESP2 by interrupt handlers SSO ESPO 4 All other Tss fields ignored Previous lask Link Reserved bits Set to o Exception Entry Mechanism Kernel>kernel Interrupted Procedures and Handler's stack (New State) — ESP Before unchanged EFLAGS Transfer to handler ESP (new frame pushed EIP CS: EIP (from IDT Error Code ESP After Transfer to handler User> kernel Interrupted Procedures Handler' s stack Stack ESP Before (New State) Transfer to handler SS:ESP TSS SSO: espO ESP EFLAGS CS: EIP (from IDT EFLAGS: E interrupt gates: clear IF ESP Ater Error code Transfer to handler

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