Enabling 6.4-Gbps pin LPDDR5 using bandwidth Impro

文件名称: Enabling 6.4-Gbps pin LPDDR5 using bandwidth Improvement Techniques

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详细说明：PAPER_07_Enabling 6.4-Gbps pin LPDDR5 using bandwidth Improvement Techniques.pdfJuyoung Kim received the B.s. degrees in computer science from Pusan National University, Busan, Korea, in 2006. Juyoung Kim is a senior engineer in Samsung Electronics, where he is working pre-silicon verification and post-silicon validation in the specialization of memory interface Acknowledgements The author would like to acknowledge and give spccial thanks to Chanmin Jo for his support in LPDDR5 memory channel modeling and simulation and also writing contained here. Also following individuals whose dedication was invaluable in enabling works: Joyoung Kim for carrying system test and debug with mcasurement, Sukhyun Jung for FD characterization with VNA measurement, Chan- Min Jo for performing memory off-chip simulation for PI/SI analysis, Gyoungbum Kim for leading improvement of electrical performance in package. Lastly, I'd like to give special appreciation to Sanghune Park who is the technical leader and advisor of electrical council task force for directing the enabling activities LPDDR5 WCK Clocking Scheme LPDDR5 DRAM is developed to provide higher data bandwidth with lower power compared with LPDdr4X dram. To address this technical challenge, LPDDR5 DRAM operates with reduced supply voltage bascd on wCK clocking, which is used for write and read clock source. In LPDDR4x, CK was used for read clock source, which has long clock latency. Thus WCK clocking can reduce the read clock network latency and clock power. Fig. shows the block diagram of LPDDR5 which adopts wCK clocking. WCK signals are adopted for the write and the read operation in LPDDR5 like GDDr5/6. In LPDDR4X, as the data rate increases and voltage decrease, the power noise induced jitter due to long clk to dqs delay has become the dominant factor to limit the high speed operation. In order to minimize clock to dQ delay, wCK signals are transmitted to each byte, meanwhile since wCK signals can be only transmitted during dQ operation to reduce power consumption, wCK2CK synchronization should be executed for domain cross between CK and wck signals whenever read or write commands are issued Memory Channe DRAM Controller (LPDDR5) CMDIADDR (1.6Gbps) CK t/CK c 800MHZ) WCK2CK WCK t/WCK c (3.2GHz) DIV DQ (6. gBps) DRAM Core RDQS 3.2GHz) Figure 1: Top-level block diagram of LPDDR5 WCK clocking LPDDR44X5 Interface Schemes LPDDR4/4X[1, 2 adopted LVSTL Low Voltage Swing Terminated Logic) interface, the signal swing level is about VDDQ/3. In case of Lpddr4X VddQ is 0.6V and signal swing level is about 300mV. To reduce the power LPddrs use 0. 5V VdDQ and swing level is 250mv under VSSQ-TERM condition. Also un-termination condition, the maximum signal swing voltage is limited to VDDQ-Vth. The proposed LPDdr4 driver in Fig. I has the multi- Voh level with the termination, which also can handle the voh drift control in case of the un-termination. Pre-emphasis and slew-rate control scheme are implemented for high speed interface signaling and reduce the emi for mobile devices In the case of VssQ-TERM condition, signal swing voltage is determined by the following equations Vx vds Vds (GS-Vth)2 (x-VDD+Vth)2 Rterm Rds Vds* Ron_up**(VDD-Vth) Ron_up*2*(DD-pth)2*Ron_up*(VDD-yth (VGS-Vth)2 RtermxVx2-2(Rterm(VDD-Vth)+ Ron(VDD-Vth))Vx+(DD-Vthy2*Rterm=0 An nmos pull-up driver operates in the saturation region like a source follower so no additional current source is required With this nmos pull-up driver characteristics non linear type driver configuration is possible and provides fast driving current. And it is possible to reduce a junction capacitance caused by small size of an NmoS pull-up driver In the case of a pull-down driver, a driver level converges to vssQ through the termination resistor (RTERm) and a pull-down driver operates in the linear region, so a pull-down driver contribution to drive small signaling is minor. Fig. 1 shows the various PDDR4/4X/5 interface configurations. Fig. 2 shows various LPDDR4/4X/5 signaling LPDDR4 interface schmes PHY P Memory DDQFO 6V VDDQ=1.1V VDD2=1.1V VDD2=1.1 VDDQ=1.1V VDDQ=1.1V VDD2=1.1y PMOS NMOS MOS 区 Pre Driver Main Drive Main Driver Pre_Driver Pre Driver Main Driver Main Driver Pre Driver LPDDR4X interface schmes PHY Memcry PHY CDQFO6V VDDQ=0.GV VDD2=: 1V VDD2=1.1VVDDQ=0V VDCO=O GV DD2=1.1 CLPMoS MOS NMO Pre Driver Main Drver Main Driver Pre Driver Pre Driver Main Driver Main Driver Pre Drive Type1 Type2 LPDDR5 interface schmes PHY Memory DD2L=1.05V VDDQ=0.5-0.3V VDD2L=1.05V NMOS 区区 Prc Drivcr Main Drivc Main Driver Prc Drivc Prc Drivcr Main Drivc Main Driver Pro Driver Ty Type2 Figure 2: LPDDR4/4/5 interface signaling ODT Features in LPDDR5 To support high density memory, LPDDR5 support 2-rank configuration. However signal integrity(si in 2-rank configuration is not good due to the reflection noise. Large reflection is caused in memory package because one dQ pad in a package is shared with each DQ pad of two dies. To prevent reflection noise in 2-rank configuration LPDDR5 memory supports non-target OdT feature which mitigate the reflection noise to improve SI at high frequency opcration. Fig. 4 shows various Odt schemes. Fig. 3 shows general 2-rank configuration equivalent circuit. L in equation( 1) means pkg. inductor and C is summation of pkg capacitance and memory Cio. R1/R2 means termination resistor value in cach memory ran C sR2 L C 尺1 V 1-02C)+1m 21 2w2LC,(1-2w2LC) WL RiR R 1 +j21wc(1-w2LC)R1区 Figure 3: Equivalent Circuit of 2-rank configuration Memory Channel Memory Controllet RC Target Rank DR十 ODT enable Non-Target Rank ODT disable Target ODT Memory Channel Memory Controller RC T arget Rank odT disable RCV arg ODT enable Non-Target ODT Memory Channel Memory Controlle RCV Target R DR ODT enabl RCY Non-target Rank ODT enable Both odt Figure 4: Termination topologies Bandwidth Improvement Techniques To increase LPDDR5 interface speed beyond the 6. 4 Gbps/pin, various bandwidth improvement techniques and P/si studies based on channel analysis will be discussed. To achieve over 6. 4 Gbps interface speed, ISI minimized tunable equalizer scheme which can support either de-emphasis or pre-emphasis is used in driver side. And also power-efficient CtLE is adopted in receiver side. Area optimized per bit offset calibration scheme is used to improve cach bits REAd valid window margin. To improve signal integrity, channel analysis results considering various off-chip conditions including discrete package will also be presented in paper. And based on this channel analysis, we suggest optimal odt schemes for both dRaM side and controller side Compared to conventional ODT scheme, proposed Odt scheme resulted in 17%VWM incensement. The measured wCK clock duty was within 43-57% at 3.2 GHz including process variation and peak-to-peak periodic jitter was less than 20ps. Another topic to discuss is low power circuit features. To save interface power and increase power efficiency, we adapted single supply driver scheme instead of conventional LVStL driver scheme, which required dual power supply for pre-driver and driver. In LVstl type driver, high voltage domain pre-driver consumes a large amount of interface power, whereas single supply driver scheme needed only vddQ power supply. By using this single supply driver scheme, substantial pre-driver power can be saved. Based on our system test results about 50% power reduction can be achieved in controller side and this leads to 20 minutes of battery time increase in Day of Use dou) scenario in smart phone More detailed inter face power analysis will be described in the full paper. Using lower threshold device in 1Onm FinFEt process, vddQ domain Dynamic voltage Frequency Scaling (dvFS) scheme is implemented Hybrid pre/de-emphasis Driver Control To achieve over 6. 4Gbps LPDDR5 interface speed various bandwidth improvement techniques are implemented in this paper. Hybrid pre-driver control scheme which can generate pre-emphasis and de-emphasis control signal. Fig. shows pre/de-emphasis driver control scheme. In Fig. 5 equalizer which adopted in driver side in the lpddr5 controller Dout Main driver Pre-emphasis Main driver Pre-emphasis enable 1Ul delay Main driver lpha X 1Ul del Main driver c-cmphasis driver DQ W/o De-emphasis re-emphasis DQ W/De-emphasis Pre-emphasis driver control De-emphasis driver contr X8 drivel De-emphasis X/ driver Pre-emph Figure 5: Driver bandwidth improvement techniques

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