DDI0487E_a_armv8_arm.pdfARMV8芯片手册，该芯片手册是从ARM官网下载的，

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详细说明：ARMV8芯片手册，该芯片手册是从ARM官网下载的，里面详细介绍的ARM处理的7种异常模式，以及ARM架构的指令集TO THE EXTENT NOT PROHIBITED BY LAW.IN NO EVENT WILL ARM BE LIABLE FOR ANY DAMAGES INCLUDING WITHOUT LIMITATION ANY DIRECT INDIRECT, SPECIAL, INCIDENTAL, PUNITIVE OR CONSEQUENTIAL DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, ARISNNG OUT OF ANY USE OF THIS DOCUMENT. EVEN IF ARM HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES This document consists solely of commercial items. You shall be responsible for ensuring that any use, duplication or disclosure of this document complies fully with any relevant export laws and regulations to assure that this document or any portion thereof is not exported, directly or indirectly, in violation of such export laws. Use of the word"partner"in reference to Arms customers is not intended to create or refer to any partnership relationship with any other company. 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You must follow the Arms trademark usage guidelines http://www.arm.com!company/policics/tradcmarks Copyright o 2013-2019 Arm Limited (or its affiliates). All rights reserved Arm Limited. Company 02557590 registered in England 110 Fulbourn Road, Cambridge, England CBl 9NJ LES-PRE-20349 In this document, where the term arm is used to refer to the company it means "Arm or any of its subsidiaries as appropriate" The term Arm can refer to versions of the Arm architecture, for example Armv8 refers to version 8 of the Arm architecture The contcxt makes it clcar when the tcrm is uscd in this way architecture profile, ARMV7-A, see the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition h of this This document describes only the armv&A architecture profile For the behaviors required by the previous versi Confidentiality Status This documcnt is Non-Confidential. Thc right to usc, copy and disclose this document may be subjcct to liccnsc restrictions in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to Product status The information in this document is final that is for a developed product Web Address http://www.arm.com Limitations of this issue This issue of the Armv8 Architecture Reference Manual contains many improvements and corrections. Validation of this document has identified the following issues that arm will address in future issues PE state on reset to AArch64 state on page D1-2290 and PE state on reset into AArch32 state on page Gl-5559 require further update. Since the reset information is present in the register descriptions, this does not affect the quality status of the release The descriptions ofread-only registers incorrectly mention reset information and will be fixed in a future release. The correct information is present in the register XML Appendix k13 Arm Pseudocode Definition requires further review and update. Since this appendix is informative, rather than being part of the architecture specification, this does not affect the quality status of this release ARM DDI 0487Ea Copyright o 2013-2019 Arm Limited or its affiliates. All rights reserved Do70919 Non-Confidential Copyright o 2013-2019 Arm Limited or its affiliates. All rights reserved ARM DD 0487Ea Non-Confidential Do70919 Contents Arm architecture reference manual army. for Armv8-A architecture profile Preface About this manual Using this manual… Conventions ∴XV Additional reading… ∴ XXVIll Feedback XXX Part a Army8 Architecture Introduction and overview Chapter a1 Introduction to the army 8 Architecture al.1 About the arm architecture A1-34 A1.2 Architecture profiles A1-36 A1.3 Armv8 architectural concepts A1-38 A1.4 Supported data types A1-4 A1.5 Advanced SIMD and floating-point support A1-51 A1.6 The arm memory mode ∴A157 Chapter A2 Army8-A Architecture extensions A2.1 Army8 architecture extensions A2-60 A2.2 Architectural features within Armv80 architecture A263 A2.3 The Armv8 Cryptographic EXtension A266 A2. 4 The army8 1 architecture extension A2-67 A2.5 The army82 architecture extension A2-70 A2. 6 The army 8.3 architecture extension A278 A2.7Thearmy8.4architectureextensionww...wwwwwwww..A2-81 A2.8 The armv85 architecture extension A2-86 ARM DDI 0487Ea Copyright o 2013-2019 Arm Limited or its affiliates. All rights reserved Do70919 Non-Confidential A2. 9 The Reliability, Availability, and serviceability Extension(RAS Extension) A290 A2.10 The Statistical Profiling EXtension(SPE) A2-91 A2. 11 The Scalable Vector EXtension(SVE) .A292 A2. 12 The activity Monitors Extension A293 A2.13 The Memory Partitioning and Monitoring(MPAM) Extension A294 Part B The AArch64 Application Level Architecture Chapter b 1 The AArch64 Application Level Programmers'Model B1.1 About the Application level programmers model B198 B1.2 Registers in AArch64 EXecution state …..B199 B1.3 Software control features and elo B110 Chapter b2 The AArch64 Application Level Memory Model B2. 1 About the arm memory model B2-108 B2.2 Atomicity in the arm architecture B2-110 B2. 3 Definition of the Armv8 memory model B2-115 B2. 4 Caches and memory hierarchy B2-133 B2.5 Alignment support B2-138 B2.6 Endian support B2.140 62.7 Memory types and attributes B2-143 B2. 8 Mismatched memory attributes B2-153 B2.9 Synchronization and semaphores B2-156 Part c The aarch64 Instruction Set Chapter C1 The A64 Instruction set C11 About the a64 instruction set .C1-170 C1.2 Structure of the A64 assembler language .C1-171 C1. 3 Address generation .C1177 C1. 4 nstruction aliases C1-180 Chapter C2 About the A64 Instruction Descriptions C2. 1 Understanding the A64 instruction descriptions C2-182 C2.2 General information about the A64 instruction descriptions C2-185 Chapter C3 A64 Instruction Set overview C3. 1 Branches, Exception generating, and System instructions .......... C3-190 C3.2 oads and stores C3-197 C3.3 Data processing-immediate C3-214 C3.4 Data processing-register C3-219 C3. 5 Data processing -SIMD and floating-point C3-227 Chapter C4 A64 Instruction Set Encoding C4.1 A64 instruction set encoding C4-252 Chapter c5 The A64 System Instruction Class C5. 1 The System instruction class encoding space C5-362 C52 Special-purpose registers C5-374 C5.3 A64 System instructions for cache maintenance C5-459 C54 A64 System instructions for address translation C5520 C55 A64 System instructions for TLB maintenance C5-543 C5.6 A64 System instructions for prediction restriction C5-739 Copyright o 2013-2019 Arm Limited or its affiliates. All rights reserved ARM DD 0487Ea Non-Confidential Do70919 Chapter C6 A64 Base Instruction Descriptions C6.1 About the a64 base instructions c6-750 C62 Alphabetical list of A64 base instructions..................... C6-753 Chapter C7 A64 Advanced SIMD and Floating- point Instruction Descriptions C7.1 About the a64 SIMD and floating- point instructions………...…..….C7-1372 C7. 2 Alphabetical list of A64 Advanced SIMD and floating-point instructions... C7-1374 Part d The AArch64 System Level Architecture Chapter d1 The AArch64 System Level Programmers'Model D1.1 Exception levels .D1-2268 D1.2 Exception terminology D12269 D1. 3 Execution state D1-2271 D1. 4 Security state D1-2272 D1.5 Virtualization D1-2274 D1.6 Registers for instruction processing and exception handling D1-2277 D1.7 Process state, PstatE .D12284 D1.8 Program counter and stack pointer alignment D12287 D1.9 Reset D1-2289 D1.10 Exception entry .. D12293 D1.11 Exception return D1-2303 D1. 12 Synchronous exception types, routing and priorities D12307 D1.13 Asynchronous exception types, routing masking and priorities D1-2316 D1.14 Configurable instruction enables and disables, and trap controls D1-2326 D1.15 System calls D1-2371 D1.16 Mechanisms for entering a low-power state.. D12372 D1.17 Self-hosted debug D12377 D1.18 Event monitors .D12379 D1.19 Interprocessing..... .D1-2380 D1.20 The effect of implementation choices on the programmers'model D12393 Chapter D2 AArch64 Self-hosted Debug About self-hosted debug D22398 D2.2 The debug exception enable controls D22402 D2.3 Routing debug exceptions D2-2403 D2. 4 Enabling debug exceptions from the current Exception level D2-2405 D2.5 The effect of powerdown on debug exceptions .D2-2407 D2.6 Summary of the routing and enabling of debug exceptions D2-2408 D2.7 Pseudocode description of debug exceptions D22410 D Q Breakpoint Instruction exceptions D22411 D2.9 Breakpoint exceptions D22413 D2. 10 Watchpoint except D22431 D2.11 Vector Catch exceptions D22445 D2. 12 Software Step exceptions .D2-2446 D2. 13 Synchronization and debug exceptions ..D2-2459 Chapter D3 AArch64 Self-hosted trace D3. 1 About self-hosted trace .D3-2462 D3.2 Prohibited regions in self-hosted trace .D3-2463 D3.3 Self-hosted trace timestamps D3-2465 D3. 4 Synchronization in self-hosted trace D3-2466 Chapter D4 The AArch64 System Level Memory Model D4. 1 About the memory system architecture D4-2468 D4.2 Address space D4-2469 D4.3 Mixed-endian support………… D4-2470 ARM DDI 0487Ea Copyright o 2013-2019 Arm Limited or its affiliates. All rights reserved Do70919 Non-Confidential D44 Cache support… D4-2471 D4.5 External aborts D4-2496 6 Memory barrier instructions D4-2498 D4.7 Pseudocode description of general memory System instructions D4-2499 Chapter D5 The AArch64 virtual Memory System Architecture D5. 1 About the Virtual Memory System Architecture(VMSA) D5-2504 D5.2 The VMsAv8-64 address translation system .D5-2512 D5 3 VMSAv8-64 translation table format descriptors D52565 D54 Memory access control….… D5-2577 D5.5 Memory region attributes D5-2599 D5.6 Virtualization host extensions D5-2609 D57 Nested virtualization D5-2615 D58 VMSAV8-64 memory aborts D5-2622 D5. 9 Translation Lookaside Butters (TLBs) D5-2632 D5.10 TLB maintenance requirements and the tlb maintenance instructions D52638 D5.11 Caches in a VMSAv8-64 implementation..... D5-2655 Chapter d6 Armv8 5 Memory Tagging Extension D6.1 Introduction D6-2660 D6.2 Allocation Tags D6-2661 D63 Tag checkin D6-2662 D6. 4 Tagged and Untagged Addresses D6-2663 D65 PE access to Allocation Tags D6-2664 D6.6 Enabling the Memory Tagging Extension..... D6-2665 D6. 7 PE handling of Tag check failure D6-2666 D6.8 PE generation of Tag Checked and Tag Unchecked accesses D6-2667 Chapter d7 The Performance Monitors extension d7. 1 About the performance monitors D7-2670 D7.2 Accuracy of the Performance Monitors D7-2673 D7 3 Behavior on overflow D7-2675 D7.4 Attributability D7-2677 D7. 5 Effect of el3 and el2 D7-2679 D7.6 Event filtering D72682 D7. 7 Performance Monitors and debug state D7-2684 D7. 8 Counter enables .D72685 D7.9 Counter access .D72687 D7, 10 PMu events and event numbers D7-2689 D7. 11 Performance Monitors Extension registers D7-2723 Chapter D8 The Activity Monitors Extension D8. 1 About the Activity Monitors Extension D82726 D8.2 Properties and behavior of the activity monitors D8-2727 B 3 AMU events and event numbers D8-2729 Chapter D9 The Statistical Profiling Extension D9. 1 About the Statistical Profiling EXtension D9-2732 D9.2 Defining the sample population D9-2734 D9. 3 Controlling when an operation is sampled D92736 D9.4 Enabling profiling D9-2739 D9.5 Filtering sample records D92741 D9.6 The profiling data… D92742 D9.7 The Profiling Buffer D92750 D9.8 Profiling Buffer management …D9-2754 D9. 9 Synchronization and statistical Profiling D92758 Copyright o 2013-2019 Arm Limited or its affiliates. All rights reserved ARM DD 0487Ea Non-Confidential Do70919 Chapter D10 Statistical Profiling Extension Sample Record Specification D10.1 About the Statistical Profiling Extension Sample Records D10-2762 D10.2 Alphabetical list of Statistical Profiling Extension packets D10-2765 Chapter D11 The generic timer in Aarch 64 state D11.1 About the generic Timer D112790 Dl1.2 The aarch64 view of the generic timer …D11-2794 Chapter d12 AArch64 System Register Encoding D12.1 The System register encoding space D12-2800 D12.2 op0==0b10, Moves to and from debug and trace System registers D122801 D12.3 op0==0b1 1, Moves to and from non-debug System registers, Special-purpose registers D12-2803 Chapter D13 AArch64 System Register Descriptions D13. 1 About the AArch64 System registers D13-2818 D13.2 General system control registers D13-2826 D13.3 Debug registers D13-3429 D13.4 Performance Monitors registers D13-3526 D13.5 Activity Monitors registers D13-3584 D13.6 Statistical Profiling Extension registers D13-3609 D13.7 RAS registers D13-3647 D13.8 Generic Timer registers .D13-3685 Part E The AArch32 Application Level Architecture Chapter E1 The AArch32 Application Level Programmers'Model E1 1 About the Application level programmers model ....... .E1-3782 E1.2 The Application level programmers' model in AArch32 state E13783 E1.3 Advanced SIMD and floating-point instructions E1-3794 E1. 4 About the AArch 32 System register interface E1-3805 E1.5 EXceptions E1-3806 Chapter E2 The Aarch32 Application Level Memory Model E2. 1 About the Arm memory model E2-3808 E2.2 Atomicity in the Arm architecture E2-3810 E2.3 Definition of the army& memory model E2-3814 E2.4 Caches and memory hierarch .E23829 E2.5 Alignment support .E23834 E2.6 Endian support E23836 E2.7 Memory types and attributes…… E2-3840 E2. 8 Mismatched memory attributes E23850 E2.9 Synchronization and semaphores E2-3853 Part F The aarch32 Instruction sets Chapter F1 The aarch 32 Instruction Sets overview F1. 1 Support for instructions in different versions of the Arm architecture .F13866 F1.2 Unified Assembler Language F1-3867 F1.3 Branch instructions F1-3869 F1.4 Data-processing instructions F13870 F1.5 PSTATE and banked register access instructions …F13878 F1.6 Load/store instructions F1-3879 F1.7 Load/store multiple instructions F1-3882 F1.8 Miscellaneous instructions F1-3883 F1.9 Exception-generating and exception-handling instructions .F1-3885 ARM DDI 0487Ea Copyright o 2013-2019 Arm Limited or its affiliates. All rights reserved X Do70919 Non-Confidential F1.10 System register access instructions F1-3887 F1.11 Advanced sIMd and floating- point load/store instructions F13888 F1.12 Advanced SIMD and floating-point register transfer instructions F13890 F1.13 Advanced SIMD data-processing instructions F1-3891 F1.14 Floating-point data-processing instructions F13901 Chapter F2 About the T32 and A32 Instruction Descriptions F2. 1 Format of instruction descriptions F23904 F22 Standard assembler syntax fields…………….….….….……….…....123908 F2.3 Conditional execution .F23909 F2. 4 Shifts applied to a register F2-3911 F2.5 Memory accesses F2-3913 F2.6 Encoding of lists of general-purpose registers and the Pc F2-3914 F2.7 General information about the T 32 and A32 instruction descriptions F2-3915 F2.8 Additional pseudocode support for instruction descriptions F2-3928 F2.9 Additional information about Advanced SIMD and floating- point instructions. F2-3929 Ch apter F3 T32 Instruction Set Encoding F3. 1 T32 instruction set encoding F3-3936 F3.2 About the T32 Advanced SIMD and floating-point instructions and their encoding F3-4003 Chapter F4 A32 Instruction Set Encoding F4.1 A32 instruction set encoding F4-4006 F4.2 About the A32 Advanced SIMD and floating-point instructions and their encoding F4-4065 Chapter F5 T32 and A32 Base Instruction Set Instruction Descriptions F5.1 Alphabetical list of T32 and A32 base instruction set instructions F5-4068 F52 Encoding and use of banked register transfer instructions .F5-4777 Chapter F6 T32 and A32 Advanced SIMD and Floating-point Instruction Descriptions F6. 1 Alphabetical list of Advanced SIMD and floating-point instructions F64782 Part G The AArch32 System Level Architecture Chapter G1 The Aarch 32 System Level Programmers' Mode G1. 1 About the aarch 32 System level programmers mode G15470 G1.2 Exception levels G1-5471 G1.3 Exception terminology G15472 G14 Execution state G1-5474 G15 nstruction set state .G15476 G1.6 Security state ......... G15477 G1.7 Security state, Exception levels, and aarch32 execution privilege...... G1-5480 Gl8 Virtualization .G1-5482 G1. 9 AArch32 state PE modes, and general-purpose and Special-purpose registers G1-5484 G1.10 Process state, G1.11 nstruction set states G1-5499 G1.12 Handling exceptions that are taken to an Exception level using AArch32..G1-5501 G1.13 Routing of aborts taken to AArch32 state.. G1-5520 G1.14 Exception return to an Exception level using AArch32 G1-5523 G1.15 Asynchronous exception behavior for exceptions taken from AArch 32 state. G1-5528 G1.16 AArch32 state exception descriptions G1-5536 G1.17 Reset into Aarch 32 state G1-5558 G1.18 Mechanisms for entering a low-power state G1-5562 G1.19 The AArch32 System register interface .G1-5567 G1.20 Advanced SIMD and floating-point support G1-5570 G1.21 Configurable instruction enables and disables, and trap controls…………G15576 X Copyright o 2013-2019 Arm Limited or its affiliates. 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