AURORA核的使用及端口说明.pdfAurora IP核是Xilinx公司在Aurora协议和高速

文件名称: AURORA核的使用及端口说明.pdf

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详细说明：Aurora IP核是Xilinx公司在Aurora协议和高速串行收发器Rocket基础上研发出来的硬核。该核嵌入在Rocket I/O模块中，提供了简单的用户接口，极大地方便了信号的可操作性。通过IP核用户界面可以改变Rocket I/O中复杂的控制结构。Aurora IP核主要包括本地流控制、用户流控制、用户数据接口、时钟输入与时钟修正模块、高速串行收发模块和状态信息控制模块[7-8] ———————————————— 版权声明：本文为CSDN博主「树桥上多情的kevin」的原创文章，遵循 CC 4.0 BY-SA 版权协议，转载请附上原文出处链接及本声明。原文链接：https://blog.csdn.net/baidu_25816669/article/details/89181274R XILINX ALL PROGRAMMABLEn Using Vivado Lab tools.... ,106 Implementing the Example Design......................... 106 Hardware Reset FSM in the Example Design...............,...... 106 Chapter 6: Test Bench Appendix A: Verification, Compliance, and Interoperability Appendix B: Upgrading Device migration....,........ ,,,,,。,。,,113 Upgrading in the vivado design Suite ,114 Migrating Legacy LocalLink based) Aurora 64B/ 66B Cores to the axl4-Stream Aurora 64B/66B Core 116 Appendix C: Debugging Finding help on Xilinx. com............................. 123 Vivado Design Suite Debug Feature 125 Simulation Debug 。125 Hardware Debug........... 127 Design Bring-Up on the KC705 Evaluation Board ................... 133 nterface debug....… .,,,,,,,,.133 Appendix D: Generating a GT Wrapper file from the transceiver Wizard Appendix E: Additional Resources and Legal notices Xilinx resources∴,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,135 Documentation Navigator and Design Hubs ,,,。,,,,,,,,,135 References 。135 Revision History.……… ,136 Please Read: Important Legal Notices 。141 Aurora 64B/66B v11.2 www.xilinx.com Send feedback PG074Apri4,2018 XL|NⅩ IP Facts ALL PROGRAMMABLE Introduction LogiCORE IP Facts Table Core Specifics The xilinx logico rETm IP aurora 64B/66B core UltraScale+ TM is a scalable lightweight high data rate Supported link-layer protocol for high-speed seria Device Family(1) Zynq -7000 All Programmable Soc communication. The protocol is open and can Virtex-73) Kintex-73) be implemented using Xilinx device echnology User AX 4-Stream Interfaces The vivado design Suite produces source Resources(4) Performance and Resource Utilization web page code for aurora 64B/66b cores. the cores can Provided with core be simplex or full-duplex, and feature one of Design Files Ve erling two simple user interfaces and optional flow Example control verilog⑤5) Design Verilog Features Constraints ile Xilinx Design Constraints(XDC) General-purpose data channels with Simulation Source hdl with securelp transceiver simulation throughput range from 500 Mb/s to over Model models 400 Gb/s Supported Supports up to 16 consecutively bonded 7 N/A S/W Driver series gtX/GTH, UltraScaleTM gTH/GTy or UltraScale+M gth/gty transceivers Tested Design Flows(6) The gt subcore is also available outside the Design Aurora core Entry Vivado⑧ Design Suite Aurora 64B/66B protocol specification v1.3 Simulatio For supported simulators, see the compliant(64B/66B encoding) Xilinx Design Tools: Release Notes Guide Synthe Vivado Synthesis Low resource cost with very low(3%) transmission overhead Support Easy-to-use AX14-Stream based framing Provided by Xilinx at the Xilinx Support web page and flow control interfaces Automatically initializes and maintains the Notes: channe 1. For a complete list of supported devices and configurations see the vivado IP catalog and associated FPGA Datasheets Full-duplex or simplex operation 2. For more information see the virtex ultrascale fpgas data 32-bit Cyclic redundancy Check( Cro) for Sheet: DC and AC Switching Characteristics(DS893)[Ref 1] user data and Kintex Ultra Scale fpgas data sheet dc and ac Switching Characteristics(DS892)[Ref 2] Kintex and virtex Added support for the Simplex Auto Link UltraScale+ FPGAs Data Sheets: DC and AC Switching Recovery feature Characteristics(DS922)[Ref 28] and(DS923)[Ref 29 Supports rX polarity inversion 3. For more information see the 7 Series fPgas overview (DS180)[Ref 3]. and the Ultrascale architecture and Product Big endian/little endian AX14-Stream user Overview(DS890)[Ref 4 interface 4. For more complete performance data, see Performance, Fully compliant aXl4-Lite DRP interface page 9 5. the iP core is delivered as verilog source code. a Configurable drp init clock mixed-language simulator is required for example design Single-ended or differential clocking simulation because of subcore dependencies options for gtrefclK and core INIT_CLK 6. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide Aurora 64B/66B v11.2 www.xilinx.com end seedlac PG074Apri4,2018 Product specification ⅩL|NX ALL PROGRAMMABLE Chapter 1 OverⅰeW This product guide describes the function and operation of the logiCoRETM IP Aurora 64B/66B core and provides information about designing, customizing, and implementing the core Aurora 64B/66B is a lightweight, serial communications protocol for multi-gigabit links (Figure 1-1). It is used to transfer data between devices using one or many GTX, GTH or GTY transceivers. Connections can be full-duplex(data in both directions)or simplex(data in either one of the directions) The Aurora 64B/ 66B core supports the amba protocol AX14-Stream user interface. It implements the Aurora 64B/66B protocol using the high-speed serial GTX, GTH or GTY transceivers in applicable UltraScale+, UltraScale TM, Zyng 8-7000, Virtex-7, and Kintex8-7 devices. a single instance of aurora 64B/66B core can use up to 16 valid consecutive lanes on GTX, GTH or GTY transceivers running at any supported line rate to provide a low-cost, general-purpose, data channel with throughput from 500 Mb/s to over 400 Gb/s Aurora 64B/66B cores are verified for protocol compliance using an array of automated simulation tests Aurora channe Partners Aurora aurora Use Interface Aurora Interface 64B/66B Application 64B66B Application Core ore User data 64B/66B User Data Figure 1-1: Aurora 64B/66B Channel Overview Aurora 64B/66B v11.2 www.xilinx.com Send feedback PG074Apri4,2018 xⅪL|NX Chapter 1: Overview Aurora 64B/66b cores automatically initialize a channel when they are connected to an Aurora 64B/66B channel partner. After initialization, applications can pass data across the channel as frames or streams of data. Aurora 64B/66B frames can be of any size, and can be interrupted any time by high priority requests. Gaps between valid data bytes are automatically filled with idles to maintain lock and prevent excessive electromagnetic nterference. Flow control is optional in Aurora 64B/66B, and can be used to throttle the link partner transmit data rate, or to send brief, high-priority messages through the channel Streams are implemented in Aurora 64B/66B as a single, unending frame. Whenever data is not being transmitted idles are transmitted to keep the link alive. Excessive bit errors, disconnections, or equipment failures cause the core to reset and attempt to initialize a new channel. The Aurora 64B/66B core can support a maximum of two symbols skew in the receipt of a multi-lane channel. the aurora 64B/66B protocol uses 64B/66B encoding. The 64B/66B encoding offers theoretical improved performance because of its very low (3%) transmission overhead, compared to 25% overhead for 8B/10B encoding RECOMMENDED 1. Although the Aurora 64B/66B core is a fully-verified solution, the challenge associated with implementing a complete design varies depending on the configuration and functionality of the application. For best results, prior experience in building high-performance, pipelined fpGa designs using Xilinx implementation tools and Xilinx Design Constraints(XDC) user constraints files is recommended 2. Consult the PcB design requirements information in the UltraScale FPGAs GTH Transceivers User Guide(UG576)[Ref 5], UltraScale fPgas gtr transceivers User Guide (UG578)[Ref 61, and 7 Series FPGAs GTX/GTH Transceivers User Guide(UG476)[Ref 71 Contact your local xilinx representative for a closer review and estimation for your specific reguirements Applications Aurora 64B/66B cores can be used in a wide variety of applications because of their low resource cost, scalable throughput, and flexible data interface. Examples of aurora 64 B/66B core applications include Chip-to-chip links: Replacing parallel connections between chips with high-speed serial connections can sig nificantly reduce the number of traces and layers required on a pcB Board-to-board and backplane links: Aurora 64B 66B uses standard 64B /66B encoding, which is the preferred encoding scheme for 10 Gigabit Ethernet, making it compatible with many existing hardware standards for cables and backplanes. Aurora 64B/66B can be scaled, both in line rate and channel width to allow inexpensive legacy hardware to be used in new, high-performance systems Aurora 64B/66B v11.2 www.xilinx.com Send feedback PG074Apri4,2018 R XILINX Chapter 1: Overview ALL PROGRAMMABLE Simplex connections(unidirectional): The Aurora 64B/66B simplex protocol provides unidirectional channel initialization, making it possible to use the gtX, gTh and GTY transceivers when a back channel is not available and to reduce costs due to unused 川- duplex resources. Unsupported Features AXl4-Stream non-strict aligned mode is not supported in the Aurora 64B/ 66B core GTP and gtZ type transceivers of 7 series devices are not supported in the aurora 64B/66B core Aurora 64B/66B supports UFC feature only in GTYE3/GTYE4 devices up to 16. 375G ynamic switching of Line rates in case of gtHE4/ GTYE4 and CPLL configurations using DRP's might not work as expected because of the updates made around GTHE4/GTYE4 CPLL Calibration module inside the gtwizard_ultrascale IP For more information see UltraScale fPgas transceivers Wizard(Pg 182)[Ref 271 Licensing and ordering This Xilinx LogiCoRE iP module is provided at no additional cost with the Xilinx vivado Design Suite under the terms of the Xilinx End User License. Information about this and other Xilinx logicore iP modules is available at the Xilinx Intellectual property page. For information about pricing and availability of other Xilinx logicoRE IP modules and tools, contact your local Xilinx sales representative For more information, visit the Aurora 64B/66B product page Aurora 64B/66B v11.2 www.xilinx.com Send feedback PG074Apri4,2018 ⅩL|NX ALL PROGRAMMABLEIM Chapter 2 Product Specification Figure 2-1 shows a block diagram of the Aurora 64B/66B core Control Serial 1/O Interface Global Logic GTX/GTH Lane (Channel Logic GTY 1 Lane 1 Maintenance) (Lane 1) RX User GTX/GTH/ Serial 1/0 i RX Data Lane 2 GTY 2 (Framing LogIc ( Lane 2) Aurora channel Serial l/o TX User GTX/GTH/ Serial I/O I Interface Lane Lane n TX Data (Framer Logic GLYn Streaming (Lane n) Figure 2-1: Aurora 64B/66B Core Block Diagram The major functional modules of the aurora 64B/66B core are Lane logic: Each Gt transceiver is driven by an instance of the lane logic module which initializes each individual transceiver, handles the encoding and decoding of control characters, and performs error detection Global logic: The global logic module in the core performs the channel bonding for channel initialization during operation the channel keeps track of the not ready idle characters defined by the aurora 64B/66B protocol and monitors all the lane logic modules for errors RX user interface: The aX14-Stream receive(rX)user interface moves data from the channel to the application and also performs flow control functions TX user interface: The aXl4-Stream transmit (TX)user interface moves data from the application to the channel and also performs flow control tX functions. the standard clock compensation module is embedded inside the core. This module controls periodic transmission of the clock compensation( Cc)character Aurora 64B/66B v11.2 www.xilinx.com Send feedback PG074Apri4,2018 R XILINX Chapter 2: Product Specification ALL PROGRAMMABLE Performance This section details the performance information for various core configurations Maximum Frequencies The maximum frequency of the core operation is dependent on the line rates supported and the speed grade of the devices Latency For a default single lane configuration, latency through an Aurora 64B/66B core is caused by pipeline delays through the protocol engine(pe)and through the gtX and gth transceivers. The PE pipeline delay increases as the aXl4-Stream interface width increases The transceiver delays are determined by the transceiver features This section outlines a method of measuring the latency for the aurora 64 B/ 66b core AXl4-Stream user interface in terms of user clk cycles for Zynq 8-7000, Virtex-7, and KintexR-7 device gtX, GTH transceiver-based designs and Ultra Scale TM, UltraScale+ device GTH and gtY transceiver-based designs. For the purposes of illustrating latency, the aurora 64B/66B modules are partitioned between logic in the gTX, GTH and gtY transceivers and protocol engine(PE)logic implemented in the FPGa Figure 2-2 illustrates the latency of the datapath TⅩAX| nterfac TX PE IX GT RX GT RX PE RX AXI Interface axi tx valid m axi rx valid Figure 2-2: Latency of the datapath Note: Figure 2-2 does not include the latency incurred due to the length of the serial connection between each side of the aurora 64 b/66b channel Aurora 64B/66B v11.2 www.xilinx.com Send feedback 9 PG074Apri4,2018 R XILINX Chapter 2: Product Specification The latency must be measured from the rising edge of the transmitteruser clk at the first assertion of s axi tx valid and s axi tx ready to the rising edge of the receiver user clk at the first assertion of m axi rx valid Figure 2-3 shows the transmitter and receiver path reference points between which the latency has been measured for the default core configuration user clk l n0 s ax tx valid 1'n1 sdx⊥ x Reddy1 +4s_axi_tx_tdata 61'h51e151e15e154el64hd 5c5d5cb05c6d5c6 64hf5.64hILLLL64H9LLLLLLILLLLLILL-64h3. +s ax tx tkeep B'nfo 岛hcQ_ i ahdo I ahcm s dx tx Ldsl user clk 110 nuuuuTnuu uLuuuurnuunLuuupuuuuupnuuuuu m aki rx valid +-+m_axi_rx tdata 54'hcfbdcfb4cfb4cfb4 64hdse #.+m_axi_rx_tkeep Bhff 8h82 2u m axi rx tlast Un0 60004.561ns 53003 535001 540001 5312921ns 2s6.76 3172.921nsh 1963.52 ns 翻e 4156.441ns 54136441ns CLK s:art 52865.681ns 2865681ns20.48ns CLK Ste 52886.161 52886161nf Figure 2-3: Latency Waveform with Reference Points Table 2-1 shows the maximum latency and the individual latency values of the contributing pipeline components for the default core configuration on 7 series gtX, gth and UltraScale, UltraScale+ GTH transceiver based devices. Latency can vary with the addition of flow controls Table 2-1: Latency for the default aurora 64B/ 66B Core Configuration Latency component user clk Cycles Logic 46 Gearbox 1or 2 Clock Com pensation 7 Maximum(total) 540r55 The pipeline delays are designed to maintain the clock speed Throughput Aurora 64B/66B core throughput depends on the number of the transceivers, transceiver type, and the target line rate of the transceivers selected For GTH transceivers, the throughput varies from 0.48 Gb/s to 254.06 Gb/s for a single-lane design to a 16-lane design, respectively. For GTY transceivers, the throughput varies from 0.455 Gb/s to 400 Gb/s with the supported line rate range of 0.5 Gb/s to 25. 7813 Gb/s. The maximum throughput for GTY may not be accurate given the lane striping difference in the design when the line rate us greater than 16.375 Gb/s Aurora 64B/66B v11.2 www.xilinx.com Send feedback 10 PG074Apri4,2018

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