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SN32F707B_V2.3_EN.pdf
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详细说明： Memory configuration Timer
32KB on-chip Flash programming memory. 3 16-bit general purpose timers support up-counting,
8KB SRAM. down-counting, and center-aligned mode.
1.5KB Boot ROM 9 sets PWM
4 sets inverse PWM with programmable dead-band
Operation Frequency up to 48MHz
Working voltage 1.8V ~ 5.5VSONAY
SN32F700R Series
32-Bit Cortex-M0 Micro-Controller
Table of content
AMENDENT HISTORY
1 PRODUCT OVERVIEW
·。鲁鲁DD●·看●。。。鲁自自自D自鲁看看香·。。告D自自垂鲁··看·鲁鲁音自·。·香自看香···。鲁自D
12
1 FEATURES
1.2 SYSTEM BLOCK DIAGRAM
1.3 CLOCK GENERATION BLOCK DIAGRAM
17
1 4 PIN ASSIGNMENT
18
1. 5 PIN DESCRIPTIONS
…23
1.6 PIN CIRCUIT DIAGRAMS.….………,…,…
26
2 CENTRAL PROCESSOR UNIT
2.1 MEMORY MAP
28
2.2 SYSTEM TICK TIMER..………29
2.2.1 OPERATION
.29
2.2.2 SYSTICK USAGE HINTS AND TIPS
.30
2.2.3 SYSTICK REGISTERS
.30
2.2.3. 1 System Tick Timer Control and Status register (SYSTICK CTRL)
30
2. 2. 3. 2 System Tick Timer Reload value register(SYSTICK LOAD)
30
2.2.3.3 System Tick Timer Current value register( SYSTICK VAL)………
2.2.3. 4 System Tick Timer Calibration Value register(SYSTICK CALIB)..........31
2.3 NESTED VECTORED INTERRUPT CONTROLLER (NVIC)
32
2.3.1 INTERRUPT AND EXCEPTION VECTORS
32
2.3.2 NVIC REGISTERS
……3
2.3.2.1RQO~3 I InterTupt Set- Enable Register(NvIC_ISER)………………………33
2.3.2.2 IRQ0-31 Interrupt Clear-Enable Register (NVIC_ ICEr)
33
2.3.2.3 IRQO-31 Interrupt Set-Pending Register(NVIC ISPR)
34
2.3.2.4 IRQO3 1 Interrupt Clear-Pending register(NVIC ICPR)
34
2.3.2.5 IRQO-31 Interrupt Priority Register(NVIC IPRn)(n-0-7)
24 APPLICATION INTERRUPT AND RESET CONTROL(AIRC)………
35
2.5 CODE OPTION TABLE
36
26 UNIQUE NUMBER..…………………………36
2.7 CORE REGISTER OVERⅤlW∴…………………………37
3 SYSTEM CONTROL…
38
3.1 RESET
38
3.1.1 POWER-ON RESET(POR
38
3.1.2 WATCHDOG RESET(WDT RESET
39
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32-Bit Cortex-M0 Micro-Controller
3.1.3 BROWN-OUT RESET
39
3.1.3.1 BROWN OUT DESCRIPTION
39
3. 1.3.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION
40
3.1.3.3 BROWN-OUT RESET IMPROVEMENT
40
3.1. 4 EXTERNAL RESET
3. 1. 41 SIMPLY RC RESET CIRCUIT
··
42
3.1.4.2 diode RC RESET CIrCUit
42
3.1.4.3 ZENER DIODE RESET CIRCUIT……………………43
3.1.4.4 VOLTAGE BIAS RESET CIRCUIT
43
3. 1. 45 EXTERNAL RESET IC
14
3.1.5 SOFTWARE RESET
44
3.2 SYSTEM CLOCK
45
3. 2.1 NTERNAL RC CLOCK SOURCE
……45
3.2.1.1 Internal High- speed RC Oscillator(IHRC)….……,…
45
3.2. 1.2 Internal Low-speed RC Oscillator (ILRC
45
3.2.2 EXTERNAL CLOCK SOURCE
46
3.2.2.1 External High-speed(EHs)Clock
····.···:·:·..············
46
3.2.2.2 CRYSTAL/ CERAMIC
3.2.2. 3 External Low-speed (els) clock
47
3.2.2.4 CRYSTAL
47
3.2.2.5 Bypass Mode
48
3.2.3PLL
,48
3.2.3.1 PLL Frequency selection
··垂垂垂
48
3.2.4 SYSTEM CLOCK (SYSCLK) SELECTION.
49
3.2.5 CLOCK-OUT CAPABITITY
49
3.3 SYSTEM CONTROL REGISTERS O
3.3.1 Analog block Control register (SYSo ANBCTRL)
3.3.2 PLL control register( SYSO PLLCTRL……
50
3.3.2. 1 RECOMMEND FREQUENCY SETTING
.51
3.3.3 Clock Source Status register(SYSO CSST)
51
3.3.4 System Clock Configuration register( SYSO CLKCFG)………
3.3.5 AHB Clock Prescale register(SYSo AHBCP)
52
3.3.6 System Reset Status register (SYSO RSTST)
3.3.7 LVD Control register (SYSO LVDCTRL)
3.3.8 External RESET Pin Control register(SYSO EXRSTCTRL)
3.3.9 SWD Pin Control register(SYSO SwDCTRL)..................... 54
3.3.10 Interrupt vector Table Mapping register syso ITM
4 SYSTEM CONTROL REGISTERS 1
55
3.4.1 AHB Clock Enable register(SYSI AHBCLKEN
55
3.4.2 APB Clock Prescale register 0(SYS/ APBCP0)
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32-Bit Cortex-M0 Micro-Controller
3.4.3 APB Clock Prescale register 1(SYS/ APBCPl)
56
4 SYSTEM OPERATION MODE...mcs.ume.umc..me, 58
4.1OⅤ ERVIEV....
…58
4.2 NORMAL MODE
…………………………,…,…,………58
4.3 LOW-POWER MODES
58
43.1 SLEEP MODE
58
4.3.2 DEEP-SLEEP MODE
4.4 WAKEUP………
4.4. OVERVIEw
4.4.2 WAKEUP TIME
60
45 STATE MACHINE OF PMU
…….61
4.6 OPERATION MODE COMPARSION TABLE
4.7 PMU REGISTERS.…
63
4.7.1 Power Control register (PMU CTRL
S GENERAL PURPOSE I/ O PORT(GPIO)……
5.1OVERⅤ正W
D·垂.音
5.2 GPIO MODE
64
5.3 GPIO REGISTERS
65
5.3.1 GPIO Port n Data register(GPlOn DATA)(n=0, 1, 2, 3)
65
5.3.2 GP1O Port n Mode register(GPIOn MODE)(n=0, 1, 2, 3)
5.3.3 GPIO Port n Configuration register (GPIOn CFG)(n=0, 1, 3)
5.3.4 GP1O Port n Configuration register(GPIOn CFG)(n=2)
6
5.3.5 GPIO Port n Interrupt Sense register (GP/On Is)(n=0, 1, 2, 3).......68
5.3.6 GPIO Port n Interrupt Both-edge sense register(GPIOn IBS)(n=0, 1, 2, 3)
68
5.3.7 GPIO Port n Interrupt vent register(GPIOn IEv(n=0, 1, 2, 3)
68
5.3.8 GP1O Port n Interrupt Enable register (GPlOn IE)(n=0, 1, 2, 3)
5.3.9 GPIO Port n Raw Interrupt Status register(GPIOn RIs(n=0, 1, 2, 3)
68
5.3.10 GPIO Port n Interrupt Clear register(GPlOn IC)(n=0, 1, 2, 3)
69
5.3.11 GPIO Port n Bits Set Operation register (GPIOn BsET(n=0, 1, 2, 3)
69
5.3.12 GPIO Port n Bits Clear Operation register(GPIOn BCLR)(n=0, 1, 2, 3)
69
5.3.13 GPlO Port n Open-Drain Control register (GPIOn ODCTRL)(n=0)
.69
6 10+1 CHANNEL ANALOG TO DIGITAL CONVERTOR (ADC)
∴71
6.1OVERⅤEEW,……
6.2 ADC CONVERTING TIME
6.3 ADC CONTROL NOTICE
73
6.3.1 ADC SIGNAL
6.3.2 ADC PROGRAM
6.3.3 ADC PIN CONFIGURATION
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32-Bit Cortex-M0 Micro-Controller
6.4 ADC CIRCUIT
74
6.5 ADC REGISTERS
75
6.5.1 ADC Management register(ADC ADM
75
6.5. 2 ADC Data register (ADC ADB)
1垂,,··看·垂和.垂希·垂,···垂
76
6.5.3 Port 2 Control register(ADC P2CON)
.76
6.5. 4 AC Interrupt Enable register(ADC IE
77
6.5.5 ADC Raw Interrupt Status register (ADC RIS
7
G RAIL TO RAIL ANALOG COMPARATOR
78
7.1OⅤ ERVIEW…
78
7.2 NORMAL COMPARATOR MODE
79
7.2.l
COMPARATOR ENABLE
79
7. 2.2 CMnOUT. CMng AND CMnIF
8
7.3 COMPARATOR APPLICATION NOTICE
81
74 COMPARATOR REGISTERS………
82
7.4.1 CMP Control register(CMP CTRL
7.4.2 CMP Internal Reference Voltage Source register(CMP VIREF
82
7.4.3 CMP Output Status register(CMP Os
7.4.4 CMP Interrupt Enable register(CMP1E)……
83
7.4.5 CMP Raw Interrupt Status register (CMP RIs)
7.4.6 CMP Interrupt Clear register(CMP /C).....
84
8 16-BIT TIMER WITH CAPTURE FUNCTION
85
8.1OVERⅤTEW,.
D,垂。垂垂垂。非。垂垂
.85
8.2 FEATURES……
85
8.3 PIN DESCRIPTION
85
8.4 BLOCK DIAGRAM
86
8.5 TIMER OPERATION
87
8.5.1Ege- aligned up- counting mode……
87
8.5.2 Edge-aligned Down-counting Mode
88
8.5.3 Center-aligned Counting Mode
88
8.6 PWM
8.6.1 PwM Mode l
,89
8.6.2 PWm Mode 2
8. 7 INVERSE PWM OUTPUT WITH DEAD-BAND PERIOD
8. 8 CT16BN REGISTERS
93
8.8.1 CT16Bn Timer Control register (CT16Bn TMRCTRL(n=0, 1, 2)
8.8.2 CT16Bn Timer Counter register( CT76Bn TC)(n=0, 1, 2)
8.8.3 CT16Bn Prescale register(CT16Bn PRE)(n=0, 1, 2)
8.8.4 CT16Bn Prescale Counter register(CT16Bn PC)(n=0, 1, 2)
942
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8.8.5 CT16Bn Count Control register(CT16Bn CNTCTRL)(n=0, 1, 2)
8.8.6 CT16Bn Match Control register(CT16Bn MCTRL)(n=O)
95
8.8. 7 CT16Bn Match Control register(CT16Bn MCTRL)(n=1)
8C"l6 Bn Match Control register(C16 Bn MCTRL(-2)………97
8.8.9 CT16Bn Match register 0-3(CT16Bn MrO-3)(n=0, 1, 2)
.98
8.8.10 CT16Bn Capture Control register(CT16Bn CAPCTRL(n-O, 1, 2
98
8.8.171 CT16Bn Capture O register (CT16Bn CAP0)(n=0, 1, 2)
98
8.8.12 CT16Bn External match register(cT16Bn em(n=0)
··垂
8.8.73 CT16Bn External match register(CT16Bn Em(n=1)
99
8.8.14 CT16Bn External Match register (CT16Bn EM(n=2)
l00
8.8.15 CT16Bn PWM Control register(CT16Bn PWMCTRL(n=0)
00
8.8.16C716 Bn PwM Control register(CT16 Bn pwmctrl)(n=1)………
8.8. 17 CT16Bn PWM Control register(C116Bn PWMCTRL)(n-2)
102
8.8.18 CT16Bn Timer Raw Interrupt Status register(CTt16Bn Rls)(n=0, 1, 2)
8.8.19 CT16Bn Timer Interrupt Clear register(CT76Bn 1C(n=0, 1, 2)............104
8.8.20 CT16Bn Timer Match register 9(CT16Bn MR9)(n=0, 1, 2)
04
8.8.21 CT16Bn PWMmN Dead-band Period register(CT16Bn PWMmNDB)(n-2)......105
9 WATCHDOG TIMER(WDT)
b鲁。自。
106
9.1OVERⅤIEW
106
9.2 BLOCK DIAGRAM.…
107
9.3 WDT REGISTERS
108
9.3.1 Watchdog con/ guration register( MDT CFO)…………
l08
9.3.2 Watchdog Clock Source register(WDT CLKSOURCE)
l08
9.3.3 Watchdog Timer Constant register(WDT TC)
l08
9.3.4 Watchdog Feed register (WDT FEED)
l09
REAL-TIME CLOCK
10.1 OVERVIEW
110
10.2 FEATURES
.110
10.3 FUNCTIONAL DESCRIPTION
.110
10.3.1 INTRODUCTION
10.3.2 RESET RTC REGISTERS
0
70.33 RTC FLAG ASSERTION
/0
10.3.4 RTC OPERATION
10.4 BLOCK DIAGRAM
…1
10.5 RTC REGISTERS
,112
10.5.7 RTC Control register (RTC CTRL)
12
10.5.2 RTC Clock Source select register(RTC CLKS)
2
10.5.3 RTC Interrupt Enable register (RTC IE
…112
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32-Bit Cortex-M0 Micro-Controller
10.5.4 RTC Raw Interrupt Status register (RTC RIS
12
10.5.5 RTC Interrupt Clear register (RTC IC
l13
10.5.6 RTC Second Counter Reload value register(RTC SECCNTvI
.113
1.5.7 RlC Second count register( RTC SECCM1…....,….,……,………………13
11SPI∴,0114
11.1 OVERVIEW
.114
11.2 FEATURES
114
11.3 PIN DESCRIPTION
…114
11. 4 INTERFACE DESCRIPTION
非·非。··4垂
115
11.4.7SPr
15
11. 4.2 COMMUNICATION FLOW
I16
11. 4.2.1 SINGLE-FRAME
lL.4.2.2 MULTI- FRAME∴………………
1l6
11.5 AUTO-SEL.……
.116
11.6 SPI REGISTERS
..117
11.6.1 SPI n Control register 0(SPIn CTRLO(n=0
·画
17
11.6.2 SPI n Control register I( SPIn ctrl)(n=0).….………
118
11.6.3 SPI n Clock Divider register(SPIn ClKDIy(n=O)
n18
77.6.4 SPIn Status register (SPIn STAT(n-o
18
11.6.5 SPI n Interrupt Enable register ( SPIn IE)(n=o)
l19
11.6.6 SPI n Raw Interrupt Status register(SPIn RlS)(n=0)
19
11.6.7 SPI n Interrupt Clear register(SPn1C)(m=0.………
·········4·;:;;.·······4········4:··
l20
11.6.8 SPIn Data register(SPIn DATA)(n=o)
l20
11.6.9 SPI n Data Fetch register(SPIn DF)(n=0)
120
12I2C∴
121
12.1 OVERVIEW
121
12.2 FEATURES…
121
12.3 PIN DESCRIPTION
.122
12 4 WAVE CHARACTERISTICS
122
12.5 I2C MASTER MODES
123
12.5. MASTER TRANSMITTER MODE
l23
72. 5.2 MASTER RECEIVER MODE
23
12.53 ARBITRATION
123
12.6 I2C SLAVE MODES
124
12.6.SL4 VE TRANSMITTER MODE.……
l24
12.6.2 SLAVE RECEIVER MODE
124
12.7 I2C REGISTERS
125
12.7.1 12C n Control register (2Cn CTRL)(n=0
125
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12.7.2 12C'n Status register (2Cn STaT)(n=0)
126
12.7.3 12C n TX Data register(12Cn TXDATA)(n=0)
127
12.7.4 12C n RX Data register(12Cn RXDATA)(n=0)
127
12.7.5 I2C n Slave Address O register (12Cn SLVADDRO)(n=0)............127
12.7.6 12C n Slave Address 1-3 register (12Cn SLVADDRI3 )(n=0)
127
12.7.7 /2C n SCL High Time register(2Cn SCLHT)(n-o
28
12.7.8 12C n SCL Low Time register (2Cn SCLLT)(n=0,
128
12.7.912 n Timeout contro! register(I2Cn7OC7RL)(n=0)…………128
13 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER (UART)....... 129
13.1OVERⅤIEW
.129
13.2 FEATURES
.129
13.3 PIN DESCRIPTION
129
13.4 BLOCK DIAGRAM
130
135 BAUD RATE CALCULATION
.131
13.6 AUTO-BAUD FLOW
..132
13.61 AUTO-BAUD
·画
l32
13.6.2 AUTO-BAUD MODES
133
13.7 UART REGISTERS
…………135
73.7./ UART n Receiver Buffer register (UARTn rB)(n=0, 1)
135
13.7.2 UART'n Transmitter Holding register( UARTn TH(n=0, 1)
135
13.7.3 UART'n Divisor Latch lsB registers( ARTn DLL)(=0,1)…………13.5
13.7.4 UART'n Divisor latch MSB register(UARTn dlM)(n=0,1).…………………136
13.7.5 UART'n Interrupt enable register(UARTn le)(n=0, 1)
l36
13.7.6 UARTn Interrupt Identification register ( UARTn )(n=0, 1)
136
13. 7.7 UART'n FIFO Control register(UARTn FIFOCTRL)(n=0, 1)
l38
13. 7.8 CART'n Line Control register (UARIn LC)(n=0, 1)
l38
13.7.9 UART'n Line status register(UARTn ls(n=0, 1)
139
73 7.10 UART'n Scratch Pad register(UARTn SP)(n=0, 7)
40
13.7.11 UART n Auto-baud Control register (UARTn ABCTRL)(n=0, 1)
l40
13. 7.12 UART n Fractional Divider register (UARTn FD)(n=0, 1)............... 140
13.7.13 UART n Control register(UARI'n CTRL)(n-O, 1).............../
13.7.14 UART'n Half-duplex enable register(UARTn hEN(n=0, 1)
l42
4 FLASH
●。。。垂。DD。。。
143
14.1OVERⅤTEW
…143
14.2 EMBEDDED FLASH MEMORY.……………………………………4143
143 FEATURES
.143
14. 4 ORGANIZATION
144
14.5 READ
144
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32-Bit Cortex-M0 Micro-Controller
14.6 PROGRAM/ERASE
144
14.7 EMBEDDED BOOT LOADER
14.8 FLASH MEMORY CONTROLLER FMC)
145
14.8./ CODE SECURITY(CS
,l45
14.8.2 PROGRAM FLASH MEMORY
l46
14.83 ERASE
46
14.8.3.1 PAGE ERASE
146
14.8.3.2 MASS ERASE.…………………………………………146
14.9 READ PROTECTION
146
14.10 HW CHECKSUM
146
1411 FMC REGISTERS
147
14.11. Flash low Power Control register(FLASIT LPCTRL)
l47
14.71.2 Flash status register (FLASH STATUS
l47
14.11.3 Flash Control register (FLASH CTRL)
l47
74.77.4 Flash Data register FLASH DATA)
48
14.71.5 Flash Address register(FLASH ADDR
48
14.11.6 Flash Checksum register( FLASH CHKSUM…,…,……
l48
I SERIAL-WIRE DEBUG
149
15.1OVERⅤEW
149
152 FEATURES
149
15.3 PIN DESCRIPTION
………149
15,4 DEBUG NOTE….149
15.4.lLⅠMT4TONs
149
15.4.2 DEBUG RECOVERY
l49
15.4.3 INTERNAL PULL-UP/DOWN RESISTORS on SWD PINs
l50
16 DEVELOPMENT TOOL……151
16.1 SN-LINK-V3
152
16.2 SN32F707B STARTER-KIT
.153
17 ELECTRICAL CHARACTERISTIC
154
17.1 ABSOLUTE MAXIMUM RATING
垂D。·。垂。非。非,非·垂垂。垂垂音非非音非·音着垂
154
17.2 ELECTRICAL CHARACTERISTIC
154
17.3 CHARACTERISTIC GRAPHS
156
FLASH ROM PROGRAMMING PIN
19 PACKAGE INFORMATION
59
19.1 LQFP 48 PIN
159
19.2 QFN 46 PIN
160
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